Polycide local interconnect method and structure

Claim 2

A semiconductor device, comprising: a first transistor with first and second terminals and an insulated gate for controlling current between the first and second terminals; an isolation region adjoining one of said terminals; a second gate disposed on said isolation region; a layer of non-monocrystalline silicon above and adjacent an upper surface of said isolation region, said one of said terminals and said second gate; and a silicide layer above and adjacent said layer of non-monocrystalline silicon.

Claim 3

The device of claim 1 further comprising a second isolation region spacing a second transistor from said first transistor.

Claim 4

A semiconductor device, comprising: a first transistor with first and second terminals and an insulated gate for controlling current between the first and second terminals; an isolation region adjoining one of said terminals; a second gate disposed on said isolation region; a layer of non-monocrystalline silicon in contact with said one of said terminals and said second gate; a silicide layer in contact with said non-monocrystalline silicon layer, said silicide layer covering side surfaces of said non-monocrystalline silicon layer; a second isolation region spacing a second transistor from said first transistor; and a second non-monocrystalline silicon layer extending from the other terminal of the first transistor, over the second isolation region to a terminal of the second transistor.

Claim 5

A semiconductor device, comprising: a first transistor with first and second terminals and an insulated gate for controlling current between the first and second terminals; an isolation region adjoining one of said terminals; a second gate disposed on said isolation region; a layer of non-monocrystalline silicon in contact with said one of said terminals and said second gate; a silicide layer in contact with said non-monocrystalline silicon layer, said silicide layer covering side surfaces of said non-monocrystalline silicon layer; a second isolation region spacing a second transistor from said first transistor; and a second non-monocrystalline silicon layer extending from the other terminal of the first transistor, over the second isolation region to a terminal of the second transistor.

Claim 6

The device of claim 3, further comprising a second silicide layer extending from the other terminal of the first transistor, over the second non-monocrystalline silicon layer and the second isolation region to the terminal of the second transistor.

Claim 7

The device of claim 4 wherein the second silicide layer covers an upper surface of said second non-monocrystalline silicon layer.

Claim 8

A CMOS device, comprising: an NMOS and a PMOS transistor, each transistor having a source, a gate and a drain; a first isolation region separating the NMOS transistor from the PMOS transistor; a second isolation region adjoining the source or the drain of the NMOS transistor; a second gate disposed on said second isolation region; a non-monocrystalline silicon layer above and adjacent an upper surface of said second isolation region, said source or said drain and said second gate; and a silicide layer above and adjacent said non-monocrystalline silicon layer.

Claim 9

A CMOS device, comprising: an NMOS and a PMOS transistor, each transistor having a source, a gate and a drain; a first isolation region separating the NMOS transistor from the PMOS transistor; a second isolation region adjoining the source or the drain of the NMOS transistor; a second gate disposed on said second isolation region; a non-monocrystalline silicon layer above and adjacent an upper surface of said second isolation region, said source or said drain and said second gate; and a silicide layer above and adjacent said non-monocrystalline silicon layer.

Claim 10

The device of claim 6 wherein the silicide layer covers side surfaces of said non-monocrystalline layer.

Claim 11

The device of claim 6, further comprising a third isolation region adjoining the source or the drain of the PMOS transistor.

Claim 12

The device of claim 8, further comprising a third gate disposed on said third isolation region.

Claim 13

The device of claim 9, further comprising a second non-monocrystalline layer above and adjacent said source or said drain of the PMOS transistor and said third gate.

Claim 14

The device of claim 10, further comprising a second silicide layer above and adjacent said second non-monocrystalline layer.

Claim 15

A CMOS device, comprising: an NMOS and a PMOS transistor, each transistor having a source, a gate and a drain; a first isolation region separating the NMOS transistor from the PMOS transistor; a second isolation region adjoining the source or the drain of the NMOS transistor; a second gate disposed on said second isolation region; a non-monocrystalline silicon layer in contact with said source or said drain and at least a top surface of said second gate; a silicide layer in contact with said non-monocrystalline silicon layer, said silicide layer covering side surfaces of said non-monocrystalline layer; and a second non-monocrystalline silicon layer extending from the other of the source or the drain of the NMOS transistor, over the first isolation region to a source or drain of the PMOS transistor.

Claim 16

A CMOS device, comprising: an NMOS and a PMOS transistor, each transistor having a source, a gate and a drain; a first isolation region separating the NMOS transistor from the PMOS transistor; a second isolation region adjoining the source or the drain of the NMOS transistor; a second gate disposed on said second isolation region; a non-monocrystalline silicon layer in contact with said source or said drain and at least a top surface of said second gate; a silicide layer in contact with said non-monocrystalline silicon layer, said silicide layer covering side surfaces of said non-monocrystalline layer; and a second non-monocrystalline silicon layer extending from the other of the source or the drain of the NMOS transistor, over the first isolation region to a source or drain of the PMOS transistor.

Claim 17

The device of claim 12, further comprising a second silicide layer in contact with said second non-monocrystalline layer, said second silicide layer covering side surfaces of said second non-monocrystalline layer.

Claim 18

The device of claim 6, wherein the source and drain of the NMOS transistor are doped N- and the source and drain of the PMOS transistor are doped P-.

Claim 19

The device of claim 14, wherein a region is formed in each of the source and drain of the NMOS transistor and doped N+ and a region is formed in each of the source and drain of the PMOS transistor and doped P+.

Claim 20

The device of claim 15, wherein said silicide layer contacts said region of said source or said drain of the NMOS transistor.

Claim 21

The device of claim 16, further comprising a second non-monocrystalline layer extending from the other of the source or the drain of the NMOS transistor, over the first isolation region to a source or drain of the PMOS transistor and a second silicide layer above and adjacent said second non-monocrystalline layer.

Claim 22

The device of claim 4, further comprising a third isolation region adjoining another terminal of the second transistor.

Claim 23

The device of claim 18, further comprising a third layer of non-monocrystalline silicon in contact with said another terminal of the second transistor and a third gate.

Claim 24

The device of claim 19, further comprising a third silicide layer in contact with said third non-monocrystalline silicon layer, said third silicide layer covering side surfaces of said third non-monocrystalline silicon layer.