Method of making double-self-aligned bipolar transistor structure

Claim 1

A method of fabricating an improved bipolar transistor comprising the steps of: a) providing a silicon substrate of a first conductivity type, said substrate having a planar surface, a subcollector region of a second conductivity type formed in said substrate, an epitaxial layer of said second conductivity type formed on said planar surface of said substrate, and first and second spaced apart isolation regions extending through said epitaxial layer into said substrate, and further having an intermediate region extending through at least said epitaxial layer and further being located between and spaced apart from the first and second regions; b) forming a collector reach through region of a second conductivity type between the intermediate and second spaced apart regions; c) forming a field oxide layer upon said planar surface; d) forming a device active area window in a portion of said field oxide layer to expose said planar surface, said device active area window being positioned between the first and intermediate spaced apart regions; e) depositing a polysilicon layer upon said field oxide layer and the device active area window; f) depositing a oxide/nitride passivation layer upon said polysilicon layer; g) removing a portion of said passivation layer, said portion being that which is positioned over the field oxide layer, thereby leaving a remainder of said passivation layer over the device active area window and further exposing said polysilicon layer outside the device active area window; h) growing a passivating oxide layer exposed polysilicon layer, wherein said passivating oxide does not grow over the remainder of said oxide/nitride passivation layer and wherein a vertical bird's beak is formed on each side of the remainder of said oxide/nitride passivation layer; i) forming an extrinsic base contact in said polysilicon and said passivating oxide layer; j) stripping the remainder of said oxide/nitride passivating layer thereby exposing said polysilicon layer in the region of the device active area window; k) etching the exposed polysilicon layer down to said epitaxial layer underneath, thereby forming an emitter window having polysilicon sidewalls; l) annealing the substrate to form an extrinsic base of a prescribed depth in said epitaxial layer; m) implanting ions of the first conductivity type through the emitter window to form an intrinsic base in said epitaxial layer, the polysilicon sidewalls acting as a mask for implanting the ions; n) exposing the substrate to a prescribed pressure and temperature to form a base oxide in the emitter window, said base oxide comprising a polysilicon oxide adjacent to an active device region in the emitter window; o) forming sidewall spacers in the emitter window; p) forming an emitter polysilicon layer containing a dopant of the second conductivity type in the emitter window; q) implanting ions of the second conductivity type into said emitter polysilicon layer; r) annealing the substrate to diffuse the dopant into the epitaxial layer to form an emitter; s) forming an emitter polysilicon region; and t) opening up base and collector contact regions.

Claim 2

A method of fabricating an improved bipolar transistor comprising the steps of: a) providing a silicon substrate of a first conductivity type, said substrate having a planar surface, a subcollector region of a second conductivity type formed in said substrate, an epitaxial layer of said second conductivity type formed on said planar surface of said substrate, and first and second spaced apart isolation regions extending through said epitaxial layer into said substrate, and further having an intermediate region extending through at least said epitaxial layer and further being located between and spaced apart from the first and second regions; b) forming a collector reach through region of a second conductivity type between the intermediate and second spaced apart regions; c) forming a field oxide layer upon said planar surface; d) forming a device active area window in a portion of said field oxide layer to expose said planar surface, said device active area window being positioned between the first and intermediate spaced apart regions; e) depositing a polysilicon layer upon said field oxide layer and the device active area window; f) depositing a oxide/nitride passivation layer upon said polysilicon layer; g) removing a portion of said passivation layer, said portion being that which is positioned over the field oxide layer, thereby leaving a remainder of said passivation layer over the device active area window and further exposing said polysilicon layer outside the device active area window; h) growing a passivating oxide layer exposed polysilicon layer, wherein said passivating oxide does not grow over the remainder of said oxide/nitride passivation layer and wherein a vertical bird's beak is formed on each side of the remainder of said oxide/nitride passivation layer; i) forming an extrinsic base contact in said polysilicon and said passivating oxide layer; j) stripping the remainder of said oxide/nitride passivating layer thereby exposing said polysilicon layer in the region of the device active area window; k) etching the exposed polysilicon layer down to said epitaxial layer underneath, thereby forming an emitter window having polysilicon sidewalls; l) annealing the substrate to form an extrinsic base of a prescribed depth in said epitaxial layer; m) implanting ions of the first conductivity type through the emitter window to form an intrinsic base in said epitaxial layer, the polysilicon sidewalls acting as a mask for implanting the ions; n) exposing the substrate to a prescribed pressure and temperature to form a base oxide in the emitter window, said base oxide comprising a polysilicon oxide adjacent to an active device region in the emitter window; o) forming sidewall spacers in the emitter window; p) forming an emitter polysilicon layer containing a dopant of the second conductivity type in the emitter window; q) implanting ions of the second conductivity type into said emitter polysilicon layer; r) annealing the substrate to diffuse the dopant into the epitaxial layer to form an emitter; s) forming an emitter polysilicon region; and t) opening up base and collector contact regions.