Method of making bipolar transistor with reduced topography

Claim 1

A method of forming a bipolar transistor comprising the steps of: providing a planar silicon substrate having an epitaxial surface layer, with a predetermined epitaxial dopant concentration of a first polarity, disposed above and in contact with a buried conductive layer, doped with a predetermined conductive layer concentration of a dopant of said first polarity; removing a portion of said epitaxial layer to form a set of shallow trenches; depositing insulating material in said shallow trenches to form a set of insulating members extending downwardly from a wafer surface and separating predetermined portions of said epitaxial layer, whereby a base region and a collector region of said epitaxial layer, separated by one of said insulating members, are formed in a transistor region of said epitaxial layer; codepositing substantially undoped polysilicon and epitaxial silicon on said wafer surface forming thereby a layer of undoped polysilicon over said set of insulating members and a layer of undoped epitaxial silicon above said base region and said collector region and having a new substantially planar wafer surface; forming a layer of doped oxide doped with a predetermined oxide dopant of a second polarity opposite said first polarity above said polysilicon and epitaxial silicon; patterning said doped oxide to remove said doped oxide above said collector region; depositing a layer of nitride on said wafer; patterning said nitride to form a first base aperture above a base implant area in said base region, separated from said insulating members by at least one link region within said undoped epitaxial layer in said base region; etching a second base aperture through said doped oxide below said first base aperture to expose said base implant area having a base aperture surface in said undoped epitaxial layer above said base region, whereby said first and second base apertures have a combined base aperture sidewall; heating said wafer for a predetermined time at a predetermined temperature to diffuse said oxide dopant from said doped oxide downwardly into said polysilicon and horizontally into said link region, whereby said polysilicon and link region together form a conductive base connector for a transistor base; implanting a predetermined base dose of a predetermined base dopant of said second polarity in said base implant area having a transistor base aperture surface in said base aperture; oxidizing said base aperture surface of said base implant area; forming an insulating sidewall abutting said base aperture sidewall within said base aperture, whereby said insulating sidewall forms a diffusion barrier between said doped oxide and material disposed above said base region; forming an emitter contact member of doped polysilicon doped with an emitter dopant of said first polarity in said base aperture above said base region between said insulating sidewalls; and heating said wafer for a predetermined time at a predetermined temperature to diffuse said emitter dopant into said transistor base through said transistor base aperture surface to form an emitter.

Claim 2

A method of forming a bipolar transistor comprising the steps of: providing a planar silicon substrate having an epitaxial surface layer, with a predetermined epitaxial dopant concentration of a first polarity, disposed above and in contact with a buried conductive layer, doped with a predetermined conductive layer concentration of a dopant of said first polarity; removing a portion of said epitaxial layer to form a set of shallow trenches; depositing insulating material in said shallow trenches to form a set of insulating members extending downwardly from a wafer surface and separating predetermined portions of said epitaxial layer, whereby a base region and a collector region of said epitaxial layer, separated by one of said insulating members, are formed in a transistor region of said epitaxial layer; codepositing substantially undoped polysilicon and epitaxial silicon on said wafer surface forming thereby a layer of undoped polysilicon over said set of insulating members and a layer of undoped epitaxial silicon above said base region and said collector region and having a new substantially planar wafer surface; forming a layer of doped oxide doped with a predetermined oxide dopant of a second polarity opposite said first polarity above said polysilicon and epitaxial silicon; patterning said doped oxide to remove said doped oxide above said collector region; depositing a layer of nitride on said wafer; patterning said nitride to form a first base aperture above a base implant area in said base region, separated from said insulating members by at least one link region within said undoped epitaxial layer in said base region; etching a second base aperture through said doped oxide below said first base aperture to expose said base implant area having a base aperture surface in said undoped epitaxial layer above said base region, whereby said first and second base apertures have a combined base aperture sidewall; heating said wafer for a predetermined time at a predetermined temperature to diffuse said oxide dopant from said doped oxide downwardly into said polysilicon and horizontally into said link region, whereby said polysilicon and link region together form a conductive base connector for a transistor base; implanting a predetermined base dose of a predetermined base dopant of said second polarity in said base implant area having a transistor base aperture surface in said base aperture; oxidizing said base aperture surface of said base implant area; forming an insulating sidewall abutting said base aperture sidewall within said base aperture, whereby said insulating sidewall forms a diffusion barrier between said doped oxide and material disposed above said base region; forming an emitter contact member of doped polysilicon doped with an emitter dopant of said first polarity in said base aperture above said base region between said insulating sidewalls; and heating said wafer for a predetermined time at a predetermined temperature to diffuse said emitter dopant into said transistor base through said transistor base aperture surface to form an emitter.

Claim 8

A method according to any of claims 1-6, in which said steps of forming said first base aperture and said second base aperture are a RIE step.

Claim 9

A method according to any of claims 1 - 6, in which said steps of forming said first base aperture and said second base aperture are a RIE step followed by a wet etch step.

Claim 11

A method according to any of claims 1-6, in which said step of codepositing polysilicon and epitaxial silicon is performed at a temperature of less than 650° C.