US3929528A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fabrication of monocriptalline silicon on insulating substrates utilizing selective etching and deposition techniques
Assignee: Motorola Solutions Inc
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Filing: 1973-01-12
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Granted: 1975-12-30
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Expires: 1993-01-12
Abstract
Abstract The methods result in starting material on substrates in which dielectrically isolated integrated circuits, each including a plurality of active devices having substantial gains at high frequencies and small geometries, can be manufactured. One method utilizes a silicon wafer having a (100) crystallographic orientation, on which a P+ layer is formed. This P+ layer has an exposed high concentration surface and a relatively low concentration surface interfacing the wafer. A first insulating material is then formed on the high concentration surface and a first supporting material is formed on the insulating material. The P+ layer provides an etch retardant for an anisotropic etch which removes much of the wafer to expose a substantially planar P+ surface of relatively low concentration on which a thin layer of high quality monocrystalline silicon is epitaxially formed. If a P+ buried layer is not desired, then the process is continued by providing a second insulating layer on the epitaxial silicon with a second supporting material thereon. Next, the first supporting material, first insulating layer and the P+ layer are removed to provide starting material which does not have a P+ buried layer therein.
Inventors
- 👤 Uryon S Davidson
- 👤 Administrator By Amil J Ajamie
- 👤 James B Price
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:13
CPC Classifications
H; H10; H10W; H10W99/00; H10D; H10D99/00; H10P; H10P95/00; Y; Y10; Y10S; Y10S148/00; Y10S148/007; Y10S148/05; Y10S148/051; Y10S148/085; Y10S438/00; Y10S438/928; Y10S438/973; Y10S438/977
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
342 words
A METHOD OF MANUFACTURE FOR PROVIDING A THIN LAYER OF HIGH QUALITY MONOCRYSTALLINE SILICON ON AN INSULATING SUBSTRATE TO FORM A STARTING MATERIAL IN WHICH MONOLITHIC INTEGRATED CIRCUITS HAVING HIGH FREQUENCY ACTIVE DEVICES CAN BE FABRICATED, SUCH METHOD COMPRISING: PROVIDING A SILICON WAFER HAVING A PREDETERMINED CRYSTALLOGRAPHIC ORIENTATION AND FIRST AND SECOND SURFACES; FORMING A LAYER OF BORON DOPED SILICON HAVING A FIRST SURFACE OF A FIRST CONCENTRATION OF DOPANT ADJACENT SAID FIRST SURFACE OF SAID SILICON WAFER AND AN EXPOSED SECOND SURFACE HAVING A SECOND CONCENTRATION OF DOPANT, SAID LAYER OF DOPEN SILICON HAVING AN INTERMEDIATE PORTION BETWEEN SAID FIRST AND SECOND SURFACES HAVING A CONCENTRATION OF DOPANT INTERMEDIATE SAID FIRST AND SECOND CONCENTRATIONS, SAID INTERMEDIATE CONCENTRATION BEING SELECTED TO RETARD THE ETCH RATE OF A SELECTIVE ETCHANT; FORMING A FIRST LAYER OF INSULATING MATERIAL OVER SAID SURFACES OF SAID SILICON WAFER AND SAID LAYER OF DOPED SILICON; FORMING A FIRST SUPPORTING LAYER OVER A PORTION OF SAID FIRST LAYER OF INSULATING MATERIAL; EXPOSING SAID SECOND SURFACE OF SAID SILICON WAFER; APPLYING A SELECTIVE ETCHANT TO SID SECOND SURFACE OF SAID SILICON WAFER, SAID ETCHANT REMOVING SAID SILICON WAFER AT A FIRST RATE UNTIL A PORTION OF SAID SILICON NEAR SAID INTERMEDIATE PORTION OF SAID LAYER OF DOPED SILICON IS EXPOSED, SAID CONCENTRATION OF DOPENT OF SAID REMAINING BORON DOPED SILICON BEING SELECTED TO HAVE AN ETCH RATE WHICH IS SUBSTANTIALLY LESS THAN SAID FIRST ETCH RATE; EPITAXIALLY FORMING THE THIN LAYER OF MONOCRYSTALLINE SILICON ON SAID EXPOSED SURFACE OF SAID LAYER OF DOPED SILICON, SAID THIN LAYER OF MONOCRYSTALLINE SILICON HAVING A FIRST SURFACE AND AN EXPOSED SURFACE; FORMING A SECOND LAYER OF INSULATING MATERIAL OVER SAID EXPOSED SURFACE OF SAID THIN LAYER OF MONOCRYSTALLINE SILICON; FORMING A SECOND SUPPORTING LAYER OVER SAID SECOND LAYER OF INSULATING MATERIAL; AND SELECTIVELY REMOVING PORTIONS OF SAID FIRST SUPPORTING LAYER, SAID FIRST LAYER OF INSULATING MATERIAL AND SAID LAYER OF DOPED SILICON TO EXPOSE A SURFACE OF SAID THIN LAYER OF MONOCRYSTALLINE SILICON THROUGH WHICH FIELD EFFECT AND BIPOLAR DEVICES CAN BE FABRICATED.
Claim 2
Independent Claim
342 words
A METHOD OF MANUFACTURE FOR PROVIDING A THIN LAYER OF HIGH QUALITY MONOCRYSTALLINE SILICON ON AN INSULATING SUBSTRATE TO FORM A STARTING MATERIAL IN WHICH MONOLITHIC INTEGRATED CIRCUITS HAVING HIGH FREQUENCY ACTIVE DEVICES CAN BE FABRICATED, SUCH METHOD COMPRISING: PROVIDING A SILICON WAFER HAVING A PREDETERMINED CRYSTALLOGRAPHIC ORIENTATION AND FIRST AND SECOND SURFACES; FORMING A LAYER OF BORON DOPED SILICON HAVING A FIRST SURFACE OF A FIRST CONCENTRATION OF DOPANT ADJACENT SAID FIRST SURFACE OF SAID SILICON WAFER AND AN EXPOSED SECOND SURFACE HAVING A SECOND CONCENTRATION OF DOPANT, SAID LAYER OF DOPEN SILICON HAVING AN INTERMEDIATE PORTION BETWEEN SAID FIRST AND SECOND SURFACES HAVING A CONCENTRATION OF DOPANT INTERMEDIATE SAID FIRST AND SECOND CONCENTRATIONS, SAID INTERMEDIATE CONCENTRATION BEING SELECTED TO RETARD THE ETCH RATE OF A SELECTIVE ETCHANT; FORMING A FIRST LAYER OF INSULATING MATERIAL OVER SAID SURFACES OF SAID SILICON WAFER AND SAID LAYER OF DOPED SILICON; FORMING A FIRST SUPPORTING LAYER OVER A PORTION OF SAID FIRST LAYER OF INSULATING MATERIAL; EXPOSING SAID SECOND SURFACE OF SAID SILICON WAFER; APPLYING A SELECTIVE ETCHANT TO SID SECOND SURFACE OF SAID SILICON WAFER, SAID ETCHANT REMOVING SAID SILICON WAFER AT A FIRST RATE UNTIL A PORTION OF SAID SILICON NEAR SAID INTERMEDIATE PORTION OF SAID LAYER OF DOPED SILICON IS EXPOSED, SAID CONCENTRATION OF DOPENT OF SAID REMAINING BORON DOPED SILICON BEING SELECTED TO HAVE AN ETCH RATE WHICH IS SUBSTANTIALLY LESS THAN SAID FIRST ETCH RATE; EPITAXIALLY FORMING THE THIN LAYER OF MONOCRYSTALLINE SILICON ON SAID EXPOSED SURFACE OF SAID LAYER OF DOPED SILICON, SAID THIN LAYER OF MONOCRYSTALLINE SILICON HAVING A FIRST SURFACE AND AN EXPOSED SURFACE; FORMING A SECOND LAYER OF INSULATING MATERIAL OVER SAID EXPOSED SURFACE OF SAID THIN LAYER OF MONOCRYSTALLINE SILICON; FORMING A SECOND SUPPORTING LAYER OVER SAID SECOND LAYER OF INSULATING MATERIAL; AND SELECTIVELY REMOVING PORTIONS OF SAID FIRST SUPPORTING LAYER, SAID FIRST LAYER OF INSULATING MATERIAL AND SAID LAYER OF DOPED SILICON TO EXPOSE A SURFACE OF SAID THIN LAYER OF MONOCRYSTALLINE SILICON THROUGH WHICH FIELD EFFECT AND BIPOLAR DEVICES CAN BE FABRICATED.
Claim 3
Dependent Claim
13 words
The method of claim 1 wherein said silicon wafer has a crystallographic orientation.
Claim 4
Dependent Claim
55 words
The method of claim 1 wherein said step of forming a layer of doped silicon utilizes a boron impurity wherein said first concentration is on the order of 1 X 1017 atoms per cubic centimeter and said second concentration of said second surface is on the order of 6 X 1019 atoms per cubic centimeter.
Claim 5
Dependent Claim
16 words
The method of claim 1 wherein said layer of doped silicon is formed by epitaxial growth.
Claim 6
Dependent Claim
15 words
The method of claim 1 wherein said layer of doped silicon is formed by diffusion.
Claim 7
Dependent Claim
17 words
The method of claim 1 wherein said first layer of insulating material is comprised of silicon dioxide.
Claim 8
Dependent Claim
17 words
The method of claim 1 wherein said first layer of insulating material is comprised of silicon nitride.
Claim 9
Dependent Claim
15 words
The method of claim 1 wherein said first supporting layer is comprised of polycrystalline silicon.
Claim 10
Dependent Claim
12 words
The method of claim 1 wherein said selective etchant includes potassium hydroxide.
Claim 11
Dependent Claim
28 words
The method of claim 1 wherein said step of forming a layer of doped silicon includes diffusing a boron impurity through said first surface of said silicon wafer.
Claim 12
Dependent Claim
29 words
The method of claim 1 wherein said step of forming a layer of doped silicon includes epitaxially growing a P+ layer upon said first surface of said silicon wafer.
Claim 13
Dependent Claim
29 words
The method of claim 1 further including the step of removing some of said thin layer of monocrystalline underlying said first surface of said thin layer of monocrystalline silicon.
Claim 14
Dependent Claim
17 words
The method of claim 1 wherein said second layer of insulating material is comprised of silicon dioxide.
Claim 15
Dependent Claim
15 words
The method of claim 1 wherein said second supporting layer is comprised of polycrystalline silicon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-29 | 1979-06-30 | 1979-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-29 | 1983-06-30 | 1983-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-29 | 1987-06-30 | 1987-12-30 | $7700.00 | Window Closed / Lapsed |