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US5291603A
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Microprocessor system with multiple interrupts masked for use in electronic control or monitoring of various solid-state products
Assignee: Eaton Corp
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Filing: 1991-03-14
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Granted: 1994-03-01
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Expires: 2011-03-14
Abstract
Abstract A microprocessor used in solid state products has multiple interrupts and a single read only memory (ROM) masked for two or more product programs. The logic state of an input pin is set to select the appropriate program. If there is an error in one program or it becomes obsolete, the microprocessor does not have to be scrapped, but can be used to execute the other (another) product program. Separate interrupt selection routines for each interrupt, addressed from a common interrupt vector table, direct program execution to an interrupt branch table for the product indicated by the input pin. The product branch table contains addresses for the interrupt service routines for the selected product. The product programs are first separately linked with the interrupt branch table for the corresponding product. The common interrupt vector table and the interrupt selection routines are then linked with one product program and its interrupt branch table, before final linkage of all software components to avoid conflicts should a program be changed.
Inventors
- 👤 Charles A. Morse
- 👤 Edward C. Prather
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 08:05
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/4843
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
161 words
A digital processor system for alternatively executing a selected one of a plurality of independent application programs, said system comprising: a microprocessor having means for accepting multiple interrupts; a single read only memory (ROM) masked to store said plurality of independent application programs and to store a common interrupt vector table accessed by said microprocessor in response to an active interrupt, an interrupt selection routine for each interrupt, and an interrupt service routine for each interrupt for each of said plurality of independent application programs; and program selection means for generating a selection signal designating a selected application program for execution by the microprocessor so that the selected one of the application programs is alternatively executed; said common interrupt vector table containing addresses of said interrupt selection routines, said interrupt selection routines responding to said program selection means and directing the microprocessor to an interrupt service routine for the active interrupt for the selected application program for execution by said microprocessor.
Claim 2
Dependent Claim
161 words
A digital processor system for alternatively executing a selected one of a plurality of independent application programs, said system comprising: a microprocessor having means for accepting multiple interrupts; a single read only memory (ROM) masked to store said plurality of independent application programs and to store a common interrupt vector table accessed by said microprocessor in response to an active interrupt, an interrupt selection routine for each interrupt, and an interrupt service routine for each interrupt for each of said plurality of independent application programs; and program selection means for generating a selection signal designating a selected application program for execution by the microprocessor so that the selected one of the application programs is alternatively executed; said common interrupt vector table containing addresses of said interrupt selection routines, said interrupt selection routines responding to said program selection means and directing the microprocessor to an interrupt service routine for the active interrupt for the selected application program for execution by said microprocessor.
Claim 3
Dependent Claim
54 words
The system of claim 1 wherein said single ROM is further masked to provide a separate interrupt branch table associated with each application program, each interrupt branch table containing jump instructions for transferring execution of the interrupt by the microprocessor to an interrupt service routine for the active interrupt for the associated application program.
Claim 4
Dependent Claim
34 words
The system of claim 2 wherein said single ROM is masked to provide said interrupt branch tables which are each linked separately with the associated application program before the application programs are linked together.
Claim 5
Dependent Claim
38 words
The system of claim 3 wherein said single ROM is masked to provide said common interrupt vector table and said product selection routines linked with one of said application programs separately linked with the associated interrupt branch table.
Claim 6
Dependent Claim
44 words
The system of claim 4 including a random access memory (RAM) used by said microprocessor to store data during execution of the selected application program, said application programs being linked to provide a separate page of memory in said RAM for each application program.
Claim 7
Dependent Claim
183 words
A digital processor system for alternative use with one of two products controlled by first and second product programs respectively, said system comprising: a microprocessor accepting multiple interrupts; a single read only memory (ROM) masked to store said first and second product programs, an interrupt service routine for each of said interrupts for each of said products, a product interrupt branch table associated with each product each including branch instructions to each of said interrupt service routines for the associated product, a selection routine for each interrupt responsive to a product selection signal to select in the product interrupt branch table associated with a selected product indicated by the product selection signal a branch instruction for an active interrupt, and a common interrupt vector table accessed by the microprocessor in response to an active interrupt and containing addresses of the product selection routines, and; product selection means for generating said product selection signal indicating the selected product so that the digital processor system is alternatively used with the selected one of the two products controlled by the first or second product program, respectively.
Claim 8
Dependent Claim
183 words
A digital processor system for alternative use with one of two products controlled by first and second product programs respectively, said system comprising: a microprocessor accepting multiple interrupts; a single read only memory (ROM) masked to store said first and second product programs, an interrupt service routine for each of said interrupts for each of said products, a product interrupt branch table associated with each product each including branch instructions to each of said interrupt service routines for the associated product, a selection routine for each interrupt responsive to a product selection signal to select in the product interrupt branch table associated with a selected product indicated by the product selection signal a branch instruction for an active interrupt, and a common interrupt vector table accessed by the microprocessor in response to an active interrupt and containing addresses of the product selection routines, and; product selection means for generating said product selection signal indicating the selected product so that the digital processor system is alternatively used with the selected one of the two products controlled by the first or second product program, respectively.
Claim 9
Independent Claim
197 words
A method of masking a single ROM for use by a microprocessor accepting multiple interrupts in alternatively executing a selected one of a plurality of application programs said method comprising the steps of: providing said plurality of application programs; providing a separate interrupt service routine for each of said multiple interrupts for each of said plurality of application programs; providing a program selection routine for each of said multiple interrupts including jump instructions transferring execution by the microprocessor in response to an interrupt to an interrupt service routine for a selected application program; providing a common interrupt vector address table containing an address for each program selection routine to be accessed by said microprocessor in response to an active interrupt; linking said common interrupt vector address table and said program selection routines together with one of said application programs; linking all other application programs with the one application program linked with the common interrupt vector address table and said program selection routines; and masking said single ROM to store said linked application programs, common interrupt vector address table and program selection routines so that said microprocessor alternatively executes said selected one of said plurality of application programs.
Claim 10
Independent Claim
197 words
A method of masking a single ROM for use by a microprocessor accepting multiple interrupts in alternatively executing a selected one of a plurality of application programs said method comprising the steps of: providing said plurality of application programs; providing a separate interrupt service routine for each of said multiple interrupts for each of said plurality of application programs; providing a program selection routine for each of said multiple interrupts including jump instructions transferring execution by the microprocessor in response to an interrupt to an interrupt service routine for a selected application program; providing a common interrupt vector address table containing an address for each program selection routine to be accessed by said microprocessor in response to an active interrupt; linking said common interrupt vector address table and said program selection routines together with one of said application programs; linking all other application programs with the one application program linked with the common interrupt vector address table and said program selection routines; and masking said single ROM to store said linked application programs, common interrupt vector address table and program selection routines so that said microprocessor alternatively executes said selected one of said plurality of application programs.
Claim 11
Dependent Claim
50 words
The method of claim 7 including: providing a program interrupt branch table associated with each program containing an address for each interrupt service routine for the associated program, and wherein said program interrupt branch tables are linked separately with the associated application program before the application programs are linked together.
Claim 12
Dependent Claim
41 words
The method of claim 8 adapted for use with a microprocessor having a random access memory (RAM) and including linking said application programs together with each independent application program assigned a separate page providing full access to said random access memory.
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USPTO Annuity & Maintenance Windows
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| 3.5 Years (Year 4) | 1997-02-28 | 1997-08-30 | 1998-03-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-28 | 2001-08-30 | 2002-03-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-28 | 2005-08-30 | 2006-03-01 | $7700.00 | Window Closed / Lapsed |