US3875564A
Expired / Lapsed
US
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Programmed digital sequence controller
Assignee: Hitachi Ltd
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Filing: 1973-03-20
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Granted: 1975-04-01
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Expires: 1993-03-20
Abstract
Abstract A digital control apparatus, for performing the control according to programs selected according to the kind of controlled object, comprising a plurality of read only memories each storing at least one program; wherein required contents are selectively read from the program stored in the first one of the plurality of read only memories, so that an output signal is produced on completion of reading so as to terminate the operation of a program counter attached to the first read only memory; immediately after the termination of the operation of the program counter, the selection and reading of required contents from the program stored in the second read only memory begins; and required contents are thus successively read from the programs stored in the other read only memories in turn in a predetermined order.
Inventors
- 👤 Hisashi Thuruoka
- 👤 Takashi Kogawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 04:25
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/045; B; B25; B25J; B25J9/00; B25J9/16; B25J9/1602; B25J9/161
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
202 words
Programmed digital sequence controller comprising: a plurality of read only memories, each of said memories storing a plurality of programs, each of the programs including a plurality of different instruction commands which are selectively utilized to control an object; a plurality of first program counters, each of said first program counters being connected to a respective read only memory for indicating the address of at least one instruction command of a predetermined program stored within said read only memory so as to read out the at least one instruction command indicated; a plurality of input means, each of said input means being connected to a respective first program counter for setting the address of the at least one instruction command of the predetermined program to be selected into said program counter; output means connected to said read only memories for producing at least one output signal in response to the completion of reading out of at least a predetermined instruction command indicated by said first program counter; and a stationary sequencer responsive to the output signal from said output means for producing signals for application to said input means and for selecting said read only memory to be addressed one after another.
Claim 2
Dependent Claim
202 words
Programmed digital sequence controller comprising: a plurality of read only memories, each of said memories storing a plurality of programs, each of the programs including a plurality of different instruction commands which are selectively utilized to control an object; a plurality of first program counters, each of said first program counters being connected to a respective read only memory for indicating the address of at least one instruction command of a predetermined program stored within said read only memory so as to read out the at least one instruction command indicated; a plurality of input means, each of said input means being connected to a respective first program counter for setting the address of the at least one instruction command of the predetermined program to be selected into said program counter; output means connected to said read only memories for producing at least one output signal in response to the completion of reading out of at least a predetermined instruction command indicated by said first program counter; and a stationary sequencer responsive to the output signal from said output means for producing signals for application to said input means and for selecting said read only memory to be addressed one after another.
Claim 3
Dependent Claim
47 words
Programmed digital sequence controller according to claim 1, wherein said output means includes a second program counter connected to all of the read only memories for producing an output signal upon completion of the reading out of the indicated instruction command from a respective read only memory.
Claim 4
Dependent Claim
59 words
Programmed digital sequence controller according to claim 1, further comprising a plurality of output registers, each of said output registers being connected to a respective read only memory for storing the at least one instruction command read out from the associated read only memory, and means for controlling the object in accordance with the contents of said output registers.
Claim 5
Dependent Claim
39 words
Programmed digital sequence controller according to claim 3, wherein said output registers are connected to said output means for providing a signal thereto upon completion of reading out of a predetermined instruction command from the associated read only memory.
Claim 6
Dependent Claim
40 words
Programmed digital sequence controller according to claim 3, wherein each said output registers includes a plurality of fields, each of said fields receiving at least a predetermined one of the instruction commands read out from the associated read only memory.
Claim 7
Dependent Claim
65 words
Programmed digital sequence controller according to claim 1, further comprising a plurality of first and second output registers, each of said first and second output registers being connected to a respective read only memory for storing predetermined instruction commands read out from the associated read only memory, and means for controlling the object in accordance with the contents of said first and second output registers.
Claim 8
Dependent Claim
43 words
Programmed digital sequence controller according to claim 6, wherein each of said first and second output registers includes a plurality of fields, each of said fields arranged for storing at least one predetermined instruction command read out from the associated read only memory.
Claim 9
Dependent Claim
54 words
Programmed digital sequence controller according to claim 7, further comprising switching means connected to respective first and second output registers, said switching means being responsive to said input means for selectively actuating said first and second output registers for storing the at least one instruction command read out from the associated read only memory.
Claim 10
Dependent Claim
42 words
Programmed digital sequence controller according to claim 8, wherein two read only memories are provided and said stationary sequencer includes a flip-flop responsive to an output signal to one of said first and second registers associated with a respective read only memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-03-31 | 1978-09-30 | 1979-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-03-31 | 1982-09-30 | 1983-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-03-31 | 1986-09-30 | 1987-04-01 | $7700.00 | Window Closed / Lapsed |