Semiconductor multi-device system with logic means for controlling the operational mode of a set of input/output data bus drivers

Claim 2

A semiconductor multi-device system incorporated on a single semiconductor chip capable of interacting with off-chip peripherals, said multi-device system comprising: bus means for carrying address signals, data signals and control signals; at least one on-chip peripheral connected to said bus means; an on-chip processing unit connected to said bus means for generating onto said bus means, a read control signal and an address signal uniquely associated with one of said on-chip or off-chip peripherals; logic means connected to said bus means, for receiving said read control signal and said address signal from said processing unit, and generating at least two logic signals in response thereof; a plurality of data bus drivers responsive to said at least two logic signals generated by said logic means and connected to said bus means for driving data signals on and off said bus means, said plurality of data bus drivers selectably operating in one of at least three modes in response to said at least two logic signals; and a plurality of terminating conductors connected to said plurality of data bus drivers, said plurality of terminating conductors providing connections for said off-chip peripherals; wherein said at least three modes of said plurality of data bus drivers include: (1) an output mode wherein data signals received from said bus means are driven onto said plurality of terminating conductors, (2) an input mode wherein data signals appearing on said terminating conductors are driven onto said bus means, and (3) a high impedance mode wherein said bus means is electrically isolated from said terminating conductors; and wherein said at least two logic signals generated by said logic means cause said data bus drivers to operate in high impedance mode when said processing unit generates a read control signal and an address signal corresponding to a read operation to read data from at least one of said on-chip peripherals.

Claim 3

The multi-device system of claim 1 wherein said processing unit also generates onto said bus means an emulator signal and said logic means also receives as input said emulator signal which, when set to logic 1, causes said logic means to generate at least two logic signals which cause said data bus drivers to operate in the output mode when said on chip processing unit generates a read control signal and an address signal corresponding to a read operation to read data from at least one of said on-chip peripherals, thereby allowing said off-chip peripherals to also read the data being read by said on-chip processing unit.

Claim 4

The system of claim 1, said processing means further generating a write control signal, and said logic means further receiving said write control signal as input, and generating in response thereof, logic signals which cause said data bus drivers to operate in the output mode when said processing unit generates a write control signal and an address signal corresponding to a write operation to write data to at least one of said on-chip peripherals.

Claim 5

The system of claim 3 wherein said logic means generates logic signals which cause said data bus drivers to operate in the output mode when said processing unit generates a write control signal and an address signal corresponding to a write operation to write data to an off-chip peripheral.

Claim 6

The system of claim 1 wherein said logic means generates logic signals which cause said data bus drivers to operate in the input mode when said processing unit generates a read control signal and an address signal corresponding to a read operation to read data from an off-chip peripheral.

Claim 7

The system of claim 1 wherein said logic means further comprises a decoding means for decoding said address signals to determine whether one of said on-chip peripherals is being accessed, and if one of said on-chip peripherals is being accessed, for generating an activating control signal and transmitting said activating control signal to the particular on-chip peripheral which is being accessed to activate said on-chip peripheral.

Claim 8

A semiconductor multi-device system incorporated on a single semiconductor chip capable of interacting with off-chip components including an off-chip processing means and off-chip peripherals, said semiconductor multi-device system comprising: bus means for carrying address signals, data signals and control signals; at least one on-chip peripheral connected to said bus means; an on-chip processing unit connected to said bus means for generating onto said bus means, a read control signal, a bus acknowledge control signal which indicates that said on-chip processing unit is in control of said bus means, and an address signal uniquely associated with one of said on-chip or off-chip peripherals; logic means connected to said bus means, for receiving said read control signal, said bus acknowledge control signal, and said address signal from said processing unit, and generating at least two logic signals in response thereof; a plurality of data bus drivers responsive to said at least two logic signals generated by said logic means and connected to said bus means for driving data signals on and off said bus means, said plurality of data bus drivers selectably operating in one of at least three modes in response to said at least two logic signals; and a plurality of terminating conductors connected to said plurality of data bus drivers, said plurality of terminating conductors providing connections for said off-chip components; wherein said at least three modes of said plurality of data bus drivers include: (1) an output mode wherein data signals received from said bus means are driven onto said plurality of terminating conductors, (2) an input mode wherein data signals appearing on said terminating conductors are driven onto said bus means, and (3) a high impedance mode wherein said bus means is electrically isolated from said terminating conductors; and wherein said at least two logic signals generated by said logic means cause said data bus drivers to operate in high impedance mode when said processing unit generates a read control signal, a bus acknowledge control signal and an address signal corresponding to a read operation to read data from at least one of said on-chip peripherals.

Claim 9

A semiconductor multi-device system incorporated on a single semiconductor chip capable of interacting with off-chip components including an off-chip processing means and off-chip peripherals, said semiconductor multi-device system comprising: bus means for carrying address signals, data signals and control signals; at least one on-chip peripheral connected to said bus means; an on-chip processing unit connected to said bus means for generating onto said bus means, a read control signal, a bus acknowledge control signal which indicates that said on-chip processing unit is in control of said bus means, and an address signal uniquely associated with one of said on-chip or off-chip peripherals; logic means connected to said bus means, for receiving said read control signal, said bus acknowledge control signal, and said address signal from said processing unit, and generating at least two logic signals in response thereof; a plurality of data bus drivers responsive to said at least two logic signals generated by said logic means and connected to said bus means for driving data signals on and off said bus means, said plurality of data bus drivers selectably operating in one of at least three modes in response to said at least two logic signals; and a plurality of terminating conductors connected to said plurality of data bus drivers, said plurality of terminating conductors providing connections for said off-chip components; wherein said at least three modes of said plurality of data bus drivers include: (1) an output mode wherein data signals received from said bus means are driven onto said plurality of terminating conductors, (2) an input mode wherein data signals appearing on said terminating conductors are driven onto said bus means, and (3) a high impedance mode wherein said bus means is electrically isolated from said terminating conductors; and wherein said at least two logic signals generated by said logic means cause said data bus drivers to operate in high impedance mode when said processing unit generates a read control signal, a bus acknowledge control signal and an address signal corresponding to a read operation to read data from at least one of said on-chip peripherals.

Claim 10

The multi-device system of claim 7 wherein said on-chip processing unit also generates onto said bus means an emulator signal and said logic means also receives as input said emulator signal which, when set to logic 1, causes said logic means to generate at least two logic signals which cause said data bus drivers to operate in the output mode when said processing unit generates a read control signal and an address signal corresponding to a read operation to read data from at least one of said on-chip peripherals, thereby allowing said off-chip processing means and off-chip peripherals to also read the data being read by said on-chip processing unit.

Claim 11

The system of claim 7, said on-chip processing unit generating a write control signal, and said logic means further receiving said write control signal as input, and generating in response thereof logic signals which cause said data bus drivers to operate in the output mode when said on-chip processing unit generates a write control signal, a bus acknowledge control signal and an address signal corresponding to a write operation to write data to at least one of said on-chip peripherals.

Claim 12

The system of claim 9 wherein said logic means generates logic signals which cause said data bus drivers to operate in the output mode when said on-chip processing unit generates a write control signal, a bus acknowledge signal and an address signal corresponding to a write operation to write data to at least one of said off-chip peripherals.

Claim 13

The system of claim 10 wherein said logic means generates logic signals which cause said data bus drivers to operate in the input mode when said on-chip processing unit generates a read control signal, a bus acknowledge signal and an address signal corresponding to a read operation to read data from at least one of said off-chip peripherals.

Claim 14

The system of claim 11 wherein said bus acknowledge control signal indicates whether said on-chip processing unit or said off-chip processing unit is in control of said bus means, and when said bus acknowledge signal indicates that said off-chip processing unit is in control of said bus means, said logic means generates logic signals which cause said data bus drivers to operate in the high impedance mode when said off-chip processing unit generates a read control or write control signal and an address signal corresponding respectively to a read or a write operation to read or write data from or to at least one of said off-chip peripherals.

Claim 15

The system of claim 12 wherein said logic means generates logic signals which cause said data bus drivers to operate in the input mode when said off-chip processing unit generates a write control signal and an address signal corresponding to a write operation to write data to at least one of said on-chip peripherals.

Claim 16

The system of claim 13 wherein said logic means generates logic signals which cause said data bus drivers to operate in the output mode when said off-chip processing unit generates a read control signal and an address signal corresponding to a read operation to read data from at least one of said on-chip peripherals.

Claim 17

The system of claim 7 wherein said logic means further comprises a decoding means for decoding said address signals to determine whether one of said on-chip peripherals is being accessed, and if one of said on-chip peripherals is being accessed, for generating an activating control signal and transmitting said activating control signal to the particular on-chip peripheral which is being accessed to activate said on-chip peripheral.