Bus driving and decoding circuit

Claim 1

A bus driving and decoding circuit for putting on a bus of a data processing system a set of binary signals and for decoding said set of signals put on said bus, at least one said set of signals including validated signal which has a minimum propagation delay, comprising a plurality of driver elements coupled to said bus, each said driver element having a signal output coupled to said bus for inputting one of said binary signals on said bus, and a decoder coupled to said bus and having inputs connected to said bus for receiving said set of signals, said plurality of drivers comprising at least two sets, each set being implemented in a single integrated component, each integrated component having a control input for enabling the transfer at the output of the drivers in said set of signals input to said driver set, with a propagation delay intrinsically equal in all drivers of said driver set and a minimum spread from driver to driver of said driver set, characterized in that said circuit comprises: first means for jointly applying an enabling signal (ABI) to said control input of said integrated components and to the input of a first driver in each set, to obtain as output from said first driver in each set a validation signal (V1,V2) which is input to said decoder, said validation signal having a delay intrinsically equal to the propagation delay of the related set, and delay means upstream or downstream from said first driver of each set to provide each of said validation signals to said decoder with an incremental delay sufficing to overlap the propagation delay spread of the related driver set, said decoder being enabled by the joint assertion of said validation signals.