← Back to Patent Explorer
US5287055A Expired / Lapsed US ⏱️ 0.0 years remaining

Circuit for measuring current in a power MOS transistor

Assignee: Aumovio France SAS
•
Filing: 1991-01-07
•
Granted: 1994-02-15
•
Expires: 2011-01-07
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A circuit for measuring current in a power MOS transistor (M0) comprises second (M1) and third (M2) transistors in series of the same type and same technology as, but having a smaller surface than, the power transistor and arranged in parallel on the latter. The two series transistors have their gates connected to the gate of the power transistor. The current in transistor (M2) which is connected to the reference electrode of the power transistor is measured.

Inventors

  • 👤 Carlo Cini
  • 👤 Domenico Rossi
  • 👤 Marc Simon

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 22:03
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/145; G01R19/15; G01R31/00; G01R31/26; G01R31/2607; G01R31/2621; G01R31/2644; G01R19/0092

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 113 words
A circuit for measuring current in a power MOS transistor, comprising: second and third transistors in series with each other, being of the same type and same technology as, but having a smaller surface than, the power transistor and arranged in parallel with said power transistor, said series transistors having their gates connected to the gate of the power transistor, and means for measuring current in said third transistor, said third transistor being connected to the same reference potential as the source of the power transistor, wherein each said MOS transistor comprises a plurality of identical cells, said power MOS transistor having a different number of cells than said second and third transistors.
Claim 2
Dependent Claim 113 words
A circuit for measuring current in a power MOS transistor, comprising: second and third transistors in series with each other, being of the same type and same technology as, but having a smaller surface than, the power transistor and arranged in parallel with said power transistor, said series transistors having their gates connected to the gate of the power transistor, and means for measuring current in said third transistor, said third transistor being connected to the same reference potential as the source of the power transistor, wherein each said MOS transistor comprises a plurality of identical cells, said power MOS transistor having a different number of cells than said second and third transistors.
Claim 3
Dependent Claim 173 words
A circuit for measuring current in a power MOS transistor, comprising: second and third transistors in series with each other, being of the same type and same technology as, but having a smaller surface than the power transistor and arranged in parallel with said power transistor, said series transistors having their gates connected to the gate of the power transistor; and means for measuring current in said third transistor, said third transistor being connected to the same reference potential as the source of the power transistor, wherein the drain of the third MOS transistor is connected to the non-inverting input of an operational amplifier, the inverting input of which is connected to the drain of the fourth MOS transistor, whose gate is connected to the gate of the third MOS transistor, the output of the operational amplifier being connected to the gate of a fifth transistor connected in series with the fourth transistor across the terminals of a supply source, the lower terminal of the fourth transistor being connected to the reference voltage.
Claim 4
Dependent Claim 173 words
A circuit for measuring current in a power MOS transistor, comprising: second and third transistors in series with each other, being of the same type and same technology as, but having a smaller surface than the power transistor and arranged in parallel with said power transistor, said series transistors having their gates connected to the gate of the power transistor; and means for measuring current in said third transistor, said third transistor being connected to the same reference potential as the source of the power transistor, wherein the drain of the third MOS transistor is connected to the non-inverting input of an operational amplifier, the inverting input of which is connected to the drain of the fourth MOS transistor, whose gate is connected to the gate of the third MOS transistor, the output of the operational amplifier being connected to the gate of a fifth transistor connected in series with the fourth transistor across the terminals of a supply source, the lower terminal of the fourth transistor being connected to the reference voltage.
Claim 5
Dependent Claim 21 words
A circuit for measuring current according to claim 2, wherein the fourth MOS transistor is identical to the fifth MOS transistor.
Claim 6
Dependent Claim 20 words
A circuit for measuring current according to claim 2, further comprising a circuit to cancel offset of said operational amplifier.
Claim 7
Dependent Claim 36 words
A circuit for measuring current according to claim 1, wherein each said MOS transistor comprises a plurality of identical cells, said power MOS transistor having a different number of cells than said second and third transistors.
Claim 8
Dependent Claim 52 words
A circuit for measuring current according to claim 5, wherein current through said power MOS transistor differs from current through said second transistor in proportion to a ratio of a number of said identical cells in said power MOS transistor to a number of said identical cells in said second MOS transistor.
Claim 9
Dependent Claim 106 words
A circuit for measuring current in a power MOS transistor, comprising: second and third transistors in series with each other, being of the same type and same technology as, but having a smaller surface than, the power transistor and arranged in parallel with said power transistor, said series transistors having their gates connected to the gate of the power transistor, and means for measuring current in said third transistor, said third transistor being connected to the same reference potential as the source of the power transistor, wherein said current measuring means comprise a fourth MOS transistor connected as a current mirror with said third MOS transistor.
Claim 10
Dependent Claim 106 words
A circuit for measuring current in a power MOS transistor, comprising: second and third transistors in series with each other, being of the same type and same technology as, but having a smaller surface than, the power transistor and arranged in parallel with said power transistor, said series transistors having their gates connected to the gate of the power transistor, and means for measuring current in said third transistor, said third transistor being connected to the same reference potential as the source of the power transistor, wherein said current measuring means comprise a fourth MOS transistor connected as a current mirror with said third MOS transistor.

References Cited (Backward Citations)

JPS54101679A Cited
JPS5499569A Cited
US4518869A Cited
US4588950A Cited
JPS6164135A Cited
JPS6215475A Cited
EP0249325A1 Cited
US4789825A Cited
JPH0234076A Cited
JPH02103945A Cited
US5013935A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-02-14 1997-08-16 1998-02-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-02-14 2001-08-16 2002-02-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-02-14 2005-08-16 2006-02-15 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag