EP0249325A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Integrated circuit with channel length indicator
Assignee: AT&T Inc
•
Filing: 1987-05-05
•
Granted: —
•
Expires: 2007-05-05
Abstract
Abstract An integrated circuit includes first and second field effect transistors having differing channel lengths, and a comparator circuit for comparing the channel currents flowing therethrough. An excessive ratio of currents indicates "short channel" effects, which degrade performance. A signal flag indicating this condition may be provided to a test pad on the chip, or used to disable operation of the integrated circuit, or otherwise used to provide an indication.
Inventors
- 👤 John Anthony Carelli
- 👤 Robert Leonard Pritchett
- 👤 Richard Alan Pedersen
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 23:20
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/26; G01R31/2607; G01R31/2621; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/184
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
104 words
An integrated circuit comprising a plurality of field effect transistors at least one of which is designed to operate at a given nominal channel length, CHARACTERIZED in that said integrated circuit further comprises: a test field effect transistor (Tl) having a first channel length (Ll), and a reference field effect transistor (T2) having a second channel length (L2) that is large compared to said first channel length; means adapted to flowing current (11, 12) through the channels of said test and said reference transistors; and means for providing a test signal that responds to the relative values of said first and second channel lengths.
Claim 2
Dependent Claim
104 words
An integrated circuit comprising a plurality of field effect transistors at least one of which is designed to operate at a given nominal channel length, CHARACTERIZED in that said integrated circuit further comprises: a test field effect transistor (Tl) having a first channel length (Ll), and a reference field effect transistor (T2) having a second channel length (L2) that is large compared to said first channel length; means adapted to flowing current (11, 12) through the channels of said test and said reference transistors; and means for providing a test signal that responds to the relative values of said first and second channel lengths.
Claim 3
Dependent Claim
41 words
The integrated circuit of claim 1 wherein said means for providing a test output signal comprises a differential amplifier also located on said integrated circuit that amplifies the difference in the drain-to-source voltages (V1, V2) between said test and reference transistors.
Claim 4
Dependent Claim
53 words
The integrated circuit of claim 1 wherein said means adapted to cause a current to flow comprises first and second load transistors (T24, T23) located on said integrated curcuit, with each load transistor connected between the drains of said test and reference transistors and a conductor adapted to supply a power supply voltage.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.