US4518869A
Expired / Lapsed
US
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Resistance comparator for switch detection
Assignee: Motorola Solutions Inc
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Filing: 1982-12-21
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Granted: 1985-05-21
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Expires: 2002-12-21
Abstract
Abstract In a resistance comparator circuit a current mirror provides a reference current to a first conduction path and a mirror current to a second conduction path. A first transistor is coupled in series with the first conduction path and a reference resistance is coupled in series with the first transistor. A second transistor is coupled in series with the second conduction path and an input resistor is placed in series with the second transistors. A bias circuit supplies a bias signal to the control nodes of the first and second transistor. A logic transition occurs when the input resistor is equal to the reference resistor or a predetermined multiple thereof.
Inventors
- 👤 Barry W. Herold
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:50
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/165; G01R19/16533; G01R19/16557; H; H03; H03K; H03K17/00; H03K17/18
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
156 words
A resistance comparator having an input and output, comprising: current source means having a reference current output coupled to a first conduction path and a current limited output coupled to a second conduction path; first current control means having a first control node for controlling the current flow in said first conduction path; means for coupling a reference resistance in series with said first conduction path; second current control means having second control node for controlling the current flow in said second conduction path; input means for coupling an input resistance in series with said second conduction path; and means for supplying a bias signal to said first and second control nodes of said first and second current control means respectively, whereby, the output is in a first logic state when said input resistance is less than a predetermined value and in a second logic state when said input resistance is greater than said predetermined value.
Claim 2
Dependent Claim
156 words
A resistance comparator having an input and output, comprising: current source means having a reference current output coupled to a first conduction path and a current limited output coupled to a second conduction path; first current control means having a first control node for controlling the current flow in said first conduction path; means for coupling a reference resistance in series with said first conduction path; second current control means having second control node for controlling the current flow in said second conduction path; input means for coupling an input resistance in series with said second conduction path; and means for supplying a bias signal to said first and second control nodes of said first and second current control means respectively, whereby, the output is in a first logic state when said input resistance is less than a predetermined value and in a second logic state when said input resistance is greater than said predetermined value.
Claim 3
Dependent Claim
20 words
The resistance comparator of claim 1, wherein said first and second current control means includes first and second transistors, respectively.
Claim 4
Dependent Claim
27 words
The resistance comparator of claim 2, wherein said current source means includes a current mirror producing a mirror current and said limited current is the mirror current.
Claim 5
Dependent Claim
45 words
The resistance comparator of claim 3, wherein said current source means includes means for limiting said mirror current at approximately the value of said reference current so that a logical voltage transition occurs at said output when said input resistance approximately equals said reference resistance.
Claim 6
Dependent Claim
48 words
The resistance comparator of claim 3, wherein said current source means includes means for limiting said mirror current at a predetermined multiple of said reference current so that a logical voltage transition occurs at said output when said input resistance is a predetermined fraction of said reference resistance.
Claim 7
Dependent Claim
48 words
The resistance comparator of claim 3, wherein said current source means includes means for limiting said mirror current at a predetermined fraction of said reference current so that a logical voltage transition occurs at said output when said input resistance is a predetermined multiple of said reference resistance.
Claim 8
Dependent Claim
22 words
The resistance comparator of claim 3, wherein said first and second control nodes are coupled together and to a single bias network.
Claim 9
Dependent Claim
18 words
The resistance comparator of claim 7, wherein said bias means includes means for temperature compensating said bias signal.
Claim 10
Dependent Claim
45 words
The resistance comparator of claim 8, wherein said second conduction path and said second transistor means are coupled together at a junction and further including a logic gate having an input connected to the junction of said second conduction path and said second transistor means.
Claim 11
Dependent Claim
13 words
The resistance comparator of claim 9, wherein said logic gate is an inverter.
Claim 12
Dependent Claim
17 words
The resistance comparator of claim 10, wherein said input resistance includes the contact resistance of a switch.
Claim 13
Dependent Claim
17 words
The resistance comparator of claims 11, wherein said first and second transistors are CMOS field effect transistors.
Claim 14
Dependent Claim
22 words
The resistance comparator of claim 4, wherein said current mirror includes third and fourth transistors, each having substantially the same electrical charateristics.
Claim 15
Dependent Claim
138 words
A resistance comparator having an input and an output, comprising: a current mirror having a reference current path and a mirror current path; a first transistor means having a first control node for controlling the current flow in said reference current path; a reference resistor coupled in series with said reference current path; a second transistor means having a second control node for controlling the current flow in said mirror current path; input means for coupling an input resistance in series with said mirror current path; and means for biasing said first and second nodes of said first and second transistor means respectively, whereby, the output is in a first logic state when said input resistance is less than a predetermined value and in a second logic state when said input resistance is greater than said predetermined value.
Claim 16
Dependent Claim
138 words
A resistance comparator having an input and an output, comprising: a current mirror having a reference current path and a mirror current path; a first transistor means having a first control node for controlling the current flow in said reference current path; a reference resistor coupled in series with said reference current path; a second transistor means having a second control node for controlling the current flow in said mirror current path; input means for coupling an input resistance in series with said mirror current path; and means for biasing said first and second nodes of said first and second transistor means respectively, whereby, the output is in a first logic state when said input resistance is less than a predetermined value and in a second logic state when said input resistance is greater than said predetermined value.
Claim 17
Dependent Claim
19 words
The resistance comparator of claim 14, wherein said control nodes are coupled together and to a single bias network.
Claim 18
Dependent Claim
45 words
The resistance comparator of claim 15 wherein said second transistor means and said mirror current path are coupled together at a junction and further including a logic gate having an input connected to the junction of said second transistor means and said mirror current path.
Claim 19
Dependent Claim
17 words
The resistance comparator of claim 16, wherein said input resistance is the contact resistance of a switch.
Claim 20
Dependent Claim
143 words
A switch detector circuit having an output, comprising: a current mirror having a reference current output and a mirror current output; a first field effect transistor operatively connected to control the current flowing from said reference current output into its drain; a reference resistor coupled in series with the source of said first field effect transistor; a second field effect transistor operatively connected to control the current flowing from said mirror current output into said second field effect transistor's drain; means for coupling a switch having contact resistance in series with the source of said second field effect transistor; and means for applying a bias voltage to the gates of said first and second field effect transistors, whereby, a logic state transition occurs at the output indicating a switch closure when the contact resistance of said switch is less than a predetermined value.
Claim 21
Dependent Claim
143 words
A switch detector circuit having an output, comprising: a current mirror having a reference current output and a mirror current output; a first field effect transistor operatively connected to control the current flowing from said reference current output into its drain; a reference resistor coupled in series with the source of said first field effect transistor; a second field effect transistor operatively connected to control the current flowing from said mirror current output into said second field effect transistor's drain; means for coupling a switch having contact resistance in series with the source of said second field effect transistor; and means for applying a bias voltage to the gates of said first and second field effect transistors, whereby, a logic state transition occurs at the output indicating a switch closure when the contact resistance of said switch is less than a predetermined value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-20 | 1988-11-19 | 1989-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-20 | 1992-11-19 | 1993-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-20 | 1996-11-19 | 1997-05-21 | $7700.00 | Window Closed / Lapsed |