Output circuit

Claim 2

An output circuit comprising a series circuit including first and second field-effect transistors connected in series between first and second nodes and an output node derived from a junction between said first and second transistors, said first and second transistors being controlled by at least one signal, a first power source, a third field-effect transistor provided between said first node and said first power source, and a control means responsive to a level of said output node for controlling a level at the gate electrode of said third transistor so as to limit a high level of said output in absolute value.

Claim 3

The circuit according to claim 1, wherein said control means includes a load element coupled between said first power source and the gate of said third transistor and a fourth field-effect transistor having a drain coupled to the gate of said third transistor, a gate supplied with a signal from said output node and a source coupled to a second power source.

Claim 4

The circuit according to claim 2, wherein said load element includes a fifth field-effect transistor inserted between said first power source and the gate of said third transistor.

Claim 5

The circuit according to claim 2, wherein said control means further includes a voltage shift means inserted between the source of said fourth transistor and said second power source.

Claim 6

The circuit according to claim 1, wherein said first and second transistors receive true and complement signals at their gates respectively.

Claim 7

The circuit according to claim 5, further including a first means for operatively setting a level of the gate of said first transistor at a predetermined level and a second means for operatively setting a level of the gate of said second transistor at said predetermined level.

Claim 8

The circuit according to claim 4, further including a third means responsive to the level of the gate of said first transistor for setting the gate of said second transistor at said predetermined level and a fourth means responsive to the level of the gate of said second transistor for setting the gate of said first transistor at said predetermined level.

Claim 9

An output circuit comprising a logic means responsive to at least one input signal for producing an output signal, said logic means including first and second power nodes, a first power source, a variable resistor means coupled between said first power node and said first power source, and control means electrically isolated from said input signal per se, said control means responsive only to said output signal for controlling said variable resistor means so as to limit a high level of said output signal in absolute value.

Claim 10

An output circuit comprising a logic means responsive to at least one input signal for producing an output signal, said logic means including first and second power nodes, a first power source, a variable resistor means coupled between said first power node and said first power source, and control means electrically isolated from said input signal per se, said control means responsive only to said output signal for controlling said variable resistor means so as to limit a high level of said output signal in absolute value.

Claim 11

The circuit according to claim 8, wherein said variable resistor means includes a first field-effect transistor coupled between said first power source and said first power node.

Claim 12

The circuit according to claim 9, wherein said control means includes a load element coupled between said first power source and a gate of said first transistor and a second field-effect transistor having a drain coupled to the gate of said first transistor, a gate supplied with said output signal and a source supplied with a second power source.

Claim 13

An output circuit comprising a logic means responsive to at least one input signal for producing an output signal, said logic means including first and second power nodes, first power source means, variable resistor means including a first field-effect transistor coupled between said first power node and said first power source means, control means electrically isolated from said input signal per se, said control means being responsive only to said output signal for controlling said variable resistor means to limit a high level of said output signal in absolute value, said control means further including a load element coupled between said first power source and a gate of said first transistor and a second field-effect transistor having a drain coupled to the gate of said first transistor, a gate supplied with said output signal and a source supplied with a second power source, said logic means further including a third field-effect transistor having a true input signal at its gate and a fourth field-effect transistor having a complement input signal at its gate connected in series between said first and second power nodes, said output signal signal being derived from a common junction between said third and fourth transistors.

Claim 14

An output circuit comprising a logic means responsive to at least one input signal for producing an output signal, said logic means including first and second power nodes, first power source means, variable resistor means including a first field-effect transistor coupled between said first power node and said first power source means, control means electrically isolated from said input signal per se, said control means being responsive only to said output signal for controlling said variable resistor means to limit a high level of said output signal in absolute value, said control means further including a load element coupled between said first power source and a gate of said first transistor and a second field-effect transistor having a drain coupled to the gate of said first transistor, a gate supplied with said output signal and a source supplied with a second power source, said logic means further including a third field-effect transistor having a true input signal at its gate and a fourth field-effect transistor having a complement input signal at its gate connected in series between said first and second power nodes, said output signal signal being derived from a common junction between said third and fourth transistors.

Claim 15

An output circuit comprising a first voltage terminal, a second voltage terminal, an output terminal, first to third nodes, a first field effect transistor coupled between said first voltage terminal and said first node and having a gate electrode coupled to said third node, a second field effect transistor coupled between said first node and said second node, a third field effect transistor coupled between said second node and said second voltage terminal, a fourth field effect transistor coupled between said first voltage terminal and said third node, a fifth field effect transistor having a drain coupled to said third node and a gate coupled to said second node, a first circuit connection coupled between a source of said fifth field effect transistor and said second voltage terminal, a second circuit connection for connecting said second node to said output terminal, and signal means responsive to at least one logic signal for controlling said second and third field effect transistors.

Claim 16

An output circuit comprising a first voltage terminal, a second voltage terminal, an output terminal, first to third nodes, a first field effect transistor coupled between said first voltage terminal and said first node and having a gate electrode coupled to said third node, a second field effect transistor coupled between said first node and said second node, a third field effect transistor coupled between said second node and said second voltage terminal, a fourth field effect transistor coupled between said first voltage terminal and said third node, a fifth field effect transistor having a drain coupled to said third node and a gate coupled to said second node, a first circuit connection coupled between a source of said fifth field effect transistor and said second voltage terminal, a second circuit connection for connecting said second node to said output terminal, and signal means responsive to at least one logic signal for controlling said second and third field effect transistors.

Claim 17

The circuit according to claim 12, further comprising a sixth field effect transistor having a drain coupled to a gate of said second field effect transistor, a gate coupled to a gate of said third field effect transistor and a source coupled to said second voltage terminal, and a seventh field effect transistor having a drain coupled to the gate of said third field effect transistor, a gate coupled to the gate of said second field effect transistor and a source coupled to said second voltage terminal.

Claim 18

The circuit according to claim 12, in which said first circuit connection includes means for shifting a voltage thereacross.

Claim 19

The circuit according to claim 12, further comprising a capacitor having a first terminal coupled to said third node and means for supplying a second terminal of said capacitor with a control signal.

Claim 20

The circuit according to claim 12, in which said signal means includes a first gate wiring for supplying the gate of said third field effect transistor with a first logic signal and a second gate wiring for supplying the gate of said second field effect transistor with a second logic signal having a phase which is opposite to the phase of said first logic signal.