Clamping arrangement for reducing the effects of noise in field effect transistor logic circuits

Claim 1

A clamping arrangement for use with a field effect transistor logic circuit having a circuit node at which a voltage level is to be established and at which noise voltage levels may appear during the course of an operating cycle for said logic circuit, said clamping arrangement comprising: a first field effect transistor having source, drain, and gate electrodes with a source-to-drain conduction path controlled by a drive voltage at its gate electrode; a second field effect transistor having source, drain, and gate electrodes with a source-to-drain conduction path controlled by a drive voltage at its gate electrode; reference means providing a reference voltage level; means connecting the conduction paths of said first and second field effect transistors in electrical series between said circuit node and said reference means whereby said transistors, when conductive, provide a shunt path for connecting said circuit node to said reference voltage level; control means establishing an operating cycle for said clamping arrangement having multiple phase intervals, said control means including a first clock signal corresponding to first and second intervals and a second clock signal corresponding to at least a third interval with said first and second clock signals being separated by a phase duration providing an inbetween interval; a precharge field effect transistor having source, drain and gate electrodes with a source-to-drain conduction path controlled by a drive voltage at its gate electrode, said precharge field effect transistor having its gate electrode connected to said circuit node and its conduction path connected between said first clock signal and the gate electrode of said first field effect transistor; means for providing a first voltage level to said circuit node and to the gate electrode of said precharge field effect transistor during said first interval, said precharge field effect transistor being rendered conductive by said first voltage level to set the gate electrode of said first field effect transistor to a corresponding first voltage level provided by said first clock signal thereby rendering said first field effect transistor conductive; means for either retaining the first voltage level on said circuit node during said second interval or establishing a second voltage level thereat, said precharge field effect transistor remaining conductive in response to said first voltage level but being rendered non-conductive by said second voltage level, said precharge field effect transistor, if nonconductive, serving to isolate the corresponding first voltage level on the gate electrode of said first field effect transistor to maintain said first field effect transistor conductive, and said precharge field effect transistor, if conductive, serving to connect the gate electrode of said first field effect transistor to the corresponding second voltage level assumed by said first clock signal during said inbetween interval to render said first field effect transistor nonconductive, whereby during said third interval following said inbeTween interval said first field effect transistor is conductive for said second voltage at said circuit node and is non-conductive for said first voltage level at said circuit node; and said second clock signal being connected to the gate electrode of said second field effect transistor for rendering said second field effect transistor conductive at least during said third interval, whereby conduction of said first and second field effect transistors during said third interval completes said shunt path to connect said circuit node and the second voltage level thereat to a corresponding second voltage level at said reference means whereby noise voltage levels appearing at said circuit node are shunted to said reference means.