US4588950A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Test system for VLSI digital circuit and method of testing
Assignee: Data Probe Corp
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Filing: 1983-11-15
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Granted: 1986-05-13
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Expires: 2003-11-15
Abstract
Abstract The conductive state of a transistor in a semiconductor integrated circuit is determined by irradiating the transistor with a radiation beam and measuring changes in load current, thereby indicating whether the transistor was conducting or non-conducting prior to irradiation. A correlated double sampling method is employed in measuring changes in load current. A load resistor in series with the device under test is capacitively coupled to a differential amplification means including a plurality of differential amplifiers with buffers connected between successive amplifiers. A system clock is stopped at a predetermined time period prior to irradiating the transistor. A bypass switch shunts the load resistor until the clock is stopped.
Inventors
- 👤 Francois J. Henley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:52
CPC Classifications
H; H10; H10D; H10D99/00; G; G01; G01R; G01R31/00; G01R31/28; G01R31/302; G01R31/308
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
138 words
A method of testing the conductive state of a transistor in a high speed semiconductor integrated circuit comprising the steps of applying electrical power through load means and bypass switch means to said integrated circuit, applying a clock signal to said integrated circuit, stopping said clock signal at a predetermined time period, opening said bypass switch means so that current flows through said load means, irradiating said transistor with a focused radiation beam, and measuring change in current applied to said integrated circuit by correlated double sampling whereby voltages at either end of said load means are capacitively coupled to differential amplification means, said measuring change including measuring current without irradiating said transistor to obtain a first measurement, measuring current while irradiating said transistor to obtain a second measurement, and subtracting said first measurement from said second measurement.
Claim 2
Independent Claim
138 words
A method of testing the conductive state of a transistor in a high speed semiconductor integrated circuit comprising the steps of applying electrical power through load means and bypass switch means to said integrated circuit, applying a clock signal to said integrated circuit, stopping said clock signal at a predetermined time period, opening said bypass switch means so that current flows through said load means, irradiating said transistor with a focused radiation beam, and measuring change in current applied to said integrated circuit by correlated double sampling whereby voltages at either end of said load means are capacitively coupled to differential amplification means, said measuring change including measuring current without irradiating said transistor to obtain a first measurement, measuring current while irradiating said transistor to obtain a second measurement, and subtracting said first measurement from said second measurement.
Claim 3
Dependent Claim
27 words
The method as defined by claim 1 and further including the step of converting an amplified analog signal from said differential amplification means to a digital signal.
Claim 4
Dependent Claim
21 words
The method as defined by claim 1 wherein said step of irradiating includes applying a focused laser beam on said transistor.
Claim 5
Dependent Claim
138 words
Test apparatus for high speed logic state analysis by determining the conduction state of a transistor in a digital semiconductor integrated circuit operating at a clock rate in excess of one megahertz comprising power supply means, load means connecting said power supply means with a semiconductor integrated circuit undergoing test, switch means for electrically bypassing said load means, laser means for selectively irradiating a transistor in said semiconductor integrated circuit, clock means for applying a clock signal to said semiconductor integrated circuit, differential amplification means, capacitive means for capacitively coupling said load means to said differential amplification means, and control means for stopping said clock means at a predetermined state time, deactivating said switch means for bypassing said load means, thereafter irradiating a transistor in said semiconductor integrated circuit, and differentially amplifying the voltage across said load means.
Claim 6
Dependent Claim
138 words
Test apparatus for high speed logic state analysis by determining the conduction state of a transistor in a digital semiconductor integrated circuit operating at a clock rate in excess of one megahertz comprising power supply means, load means connecting said power supply means with a semiconductor integrated circuit undergoing test, switch means for electrically bypassing said load means, laser means for selectively irradiating a transistor in said semiconductor integrated circuit, clock means for applying a clock signal to said semiconductor integrated circuit, differential amplification means, capacitive means for capacitively coupling said load means to said differential amplification means, and control means for stopping said clock means at a predetermined state time, deactivating said switch means for bypassing said load means, thereafter irradiating a transistor in said semiconductor integrated circuit, and differentially amplifying the voltage across said load means.
Claim 7
Dependent Claim
25 words
Test apparatus as defined by claim 4, wherein said differential amplification means includes a plurality of amplifier stages with buffer means interconnecting successive amplifier stages.
Claim 8
Dependent Claim
29 words
Test apparatus as defined by claim 5 and further including analog to digital conversion means for converting an amplified analog voltage from said load resistor to a digital signal.
Claim 9
Dependent Claim
14 words
Test apparatus as defined by claim 4 wherein said load means comprises a resistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-12 | 1989-11-11 | 1990-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-12 | 1993-11-11 | 1994-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-12 | 1997-11-11 | 1998-05-13 | $7700.00 | Window Closed / Lapsed |