Output circuit with output enabling inputs

Claim 2

An output circuit for a semiconductor integrated circuit comprising: output means for providing an output signal in accordance with an input signal; said input signal having one of a first and a second state; and control means, receiving a reference signal and a control signal delayed relative to said reference signal, for controlling a timing of occurrence of said output signal and an output impedance of said output means in accordance with combinations of said control signal and said reference signal.

Claim 3

An output circuit for a semiconductor integrated circuit, according to claim 1 comprising: said output means including a first switching means which is conductive when said first switching means receives a first output control signal in a first state, and is non-conductive when said first switching means receives said first output control signal in a second state; said output means including a second switching means which is conductive when said second switching means receives a second output control signal in said second state, and is non-conductive when said second switching means receives said second output control signal in said first state; said first and second switching means are connected in series between a first and a second potential; said output means has an output node provided at a junction between said first and said second switching means; and said first and second output control signals being produced by said control means and being responsive to combinations of states of said control signal, said reference signal, and said input signal.

Claim 4

An output circuit for a semiconductor integrated circuit comprising: output means for providing an output signal in accordance with an input signal; said input signal having one of a first and a second state; control means, receiving a control signal delayed relative to a reference signal, for controlling a timing of occurrence of said output signal in accordance with said control signal; said output means including a first switching means which is conductive when said first switching means receives a first output control signal in a first state, and is non-conductive when said first switching means receives said first output control signal in a second state; and said output means including a second switching means which is conductive when said second switching means receives a second output control signal in said second state, and is non-conductive when said second switching means receives said second output control signal in said first state; said first and second switching means being connected in series between a first and a second potential; said output means having an output node provided at a junction between said first and said second switching means; said control means including a first means for receiving said reference signal and said control signal; each of said reference and control signals having one of a first and a second state; said first means producing a signal in said first state when said control signal is in said first state; said first means producing said signal in said first state when said control and reference signals are in said second and first states, respectively; said first means producing said signal in said second state when said control and reference signals are in their second states; a second means for receiving said signal of said first means and said input signal; said second means providing said first and second output control signals in said second and first states to said first and second switching means, respectively, when said signal from said first means is in said first state; said second means providing said first and second output control signals in said first state to said first and second switching means when said signal from said first means is in said second state and said input signal is in said first state; and said second means providing said first and second output control signals in said second state to said first and second switching means when said signal from said first means in said second state and said input signal is in said second state.

Claim 5

An output circuit for a semiconductor integrated circuit comprising: output means for providing an output signal in accordance with an input signal; said input signal having one of a first and a second state; control means, receiving a control signal delayed relative to a reference signal, for controlling a timing of occurrence of said output signal in accordance with said control signal; said output means including a first switching means which is conductive when said first switching means receives a first output control signal in a first state, and is non-conductive when said first switching means receives said first output control signal in a second state; and said output means including a second switching means which is conductive when said second switching means receives a second output control signal in said second state, and is non-conductive when said second switching means receives said second output control signal in said first state; said first and second switching means being connected in series between a first and a second potential; said output means having an output node provided at a junction between said first and said second switching means; said control means including a first means for receiving said reference signal and said control signal; each of said reference and control signals having one of a first and a second state; said first means producing a signal in said first state when said control signal is in said first state; said first means producing said signal in said first state when said control and reference signals are in said second and first states, respectively; said first means producing said signal in said second state when said control and reference signals are in their second states; a second means for receiving said signal of said first means and said input signal; said second means providing said first and second output control signals in said second and first states to said first and second switching means, respectively, when said signal from said first means is in said first state; said second means providing said first and second output control signals in said first state to said first and second switching means when said signal from said first means is in said second state and said input signal is in said first state; and said second means providing said first and second output control signals in said second state to said first and second switching means when said signal from said first means in said second state and said input signal is in said second state.

Claim 6

An output circuit for a semiconductor integrated circuit, according to claim 3 wherein: said first means includes a first NAND circuit; and said second means includes an inverter, for inverting said signal of said first means from said first NAND circuit, a second NAND circuit which receives said signal from said inverter and said input signal, and a NOR circuit which receives said output signal from said first NAND circuit and said input signal.

Claim 7

An output circuit for a semiconductor integrated circuit comprising: output means for providing an output signal in accordance with an input signal; said input signal having one of a first and a second state; control means, receiving a control signal delayed relative to a reference signal, for controlling a timing of occurrence of said output signal in accordance with said control signal; said output means including a first switching means which is conductive when said first switching means receives an output control signal in a first state, and is non-conductive when said first switching means receives said output control signal in a second state; and said output means including a second switching means which is conductive when said second switching means receives said output control signal in said second state, and is non-conductive when said second switching means receives said output control signal in said first state; said first and second switching means being connected in series between a first and a second potential; said output means having an output node provided at a junction between said first and said second switching means; and said control means including a NAND circuit which receives said control signal and said input signal.

Claim 8

An output circuit for a semiconductor integrated circuit comprising: output means for providing an output signal in accordance with an input signal; said input signal having one of a first and a second state; control means, receiving a control signal delayed relative to a reference signal, for controlling a timing of occurrence of said output signal in accordance with said control signal; said output means including a first switching means which is conductive when said first switching means receives an output control signal in a first state, and is non-conductive when said first switching means receives said output control signal in a second state; and said output means including a second switching means which is conductive when said second switching means receives said output control signal in said second state, and is non-conductive when said second switching means receives said output control signal in said first state; said first and second switching means being connected in series between a first and a second potential; said output means having an output node provided at a junction between said first and said second switching means; and said control means including a NAND circuit which receives said control signal and said input signal.

Claim 9

An output circuit for a semiconductor integrated circuit comprising: output means for providing an output signal in accordance with an input signal; said input signal having one of a first and a second state; control means, receiving a control signal delayed relative to a reference signal, for controlling a timing of occurrence of said output signal in accordance with said control signal; said output means including a first switching means which is conductive when said first switching means receives an output control signal in a first state, and is non-conductive when said first switching means receives said output control signal in a second state; and said output means including a second switching means which is conductive when said second switching means receives said output control signal in said second state, and is non-conductive when said second switching means receives said output control signal in said first state; said first and second switching means being connected in series between a first and a second potential; said output means having an output node provided at a junction between said first and said second switching means; and said control means including a an exclusive OR circuit which receives said control signal and said input signal.

Claim 10

An output circuit for a semiconductor integrated circuit comprising: output means for providing an output signal in accordance with an input signal; said input signal having one of a first and a second state; control means, receiving a control signal delayed relative to a reference signal, for controlling a timing of occurrence of said output signal in accordance with said control signal; said output means including a first switching means which is conductive when said first switching means receives an output control signal in a first state, and is non-conductive when said first switching means receives said output control signal in a second state; and said output means including a second switching means which is conductive when said second switching means receives said output control signal in said second state, and is non-conductive when said second switching means receives said output control signal in said first state; said first and second switching means being connected in series between a first and a second potential; said output means having an output node provided at a junction between said first and said second switching means; and said control means including a an exclusive OR circuit which receives said control signal and said input signal.

Claim 11

An output circuit for a semiconductor integrated circuit comprising: output means for receiving an input signal having one of a first and a second state, and for providing an output signal in accordance with said input signal; storage means for receiving a first control signal having one of a first and a second state, and for storing said first control signal therein; and control means, receiving said first control signal stored in said storage means, and a second control signal having one of a first and a second state, for controlling a timing of occurrence of said output signal in said output means in response to a transition of said second control signal from said first to said second state, when said first control signal is in said first state.

Claim 12

An output circuit for a semiconductor integrated circuit comprising: output means for receiving an input signal having one of a first and a second state, and for providing an output signal in accordance with said input signal; storage means for receiving a first control signal having one of a first and a second state, and for storing said first control signal therein; and control means, receiving said first control signal stored in said storage means, and a second control signal having one of a first and a second state, for controlling a timing of occurrence of said output signal in said output means in response to a transition of said second control signal from said first to said second state, when said first control signal is in said first state.

Claim 13

An output circuit for a semiconductor integrated circuit, according to claim 7 wherein said output means includes: a first switching means which is conductive when said first switching means receives an output control signal in a first state, and is non-conductive when said first switching means receives said output control signal in a second state; a second switching means which is conductive when said second switching means receives said output control signal in said second state, and is non-conductive when said second switching means receives said output signal in said first state; said first and second switching means are connected in series between a first and a second potential; and said output means has an output node provided at a junction between said first and said second switching means.

Claim 14

An output circuit for a semiconductor integrated circuit, according to claim 8 wherein said output means includes: an OR means for receiving said first and second control signals; a first means for receiving an output signal from said OR means and a reference signal having one of a first and a second state; said first means producing said output signal in said first state when said output signal from said OR means is in said first state; said first means producing said output signal in said first state when said output signal from said OR means is in said second state and said reference signal in said first state; said first means producing said output signal in said second state when said output signal from said OR means and said reference signal are in said second state; a second means for receiving said output signal of said first means and said input signal; said second means providing said output control signal in said second and first states to said first and second switching means respectively, when said output signal from said first means is in said first state; said second means providing said output control signal in said first state to said first and second switching means when said output signal from said first means is in said second state and said input signal in said first state; and said second means providing said output control signal in said second state to said first and second switching means when said output signal from said first means is in said second state and said input signal is in said second state.

Claim 15

An output circuit for a semiconductor integrated circuit, according to claim 9 wherein: said first means includes a first NAND circuit; and said second means includes an inverter, for inverting said output signal from said first NAND circuit, a second NAND circuit which receives said output signal from said inverter and said input signal, and a NOR circuit which receives said output signal from said first NAND circuit and said input signal.

Claim 16

An output circuit for a semiconductor integrated circuit, according to claim 8 wherein said control means includes: OR means for receiving said first and second control signals; and a NAND circuit for receiving said output signal from said OR means and said input signal.

Claim 17

An output circuit for a semiconductor integrated circuit, according to claim 8 wherein said control means comprises: OR means which receives said first and second control signals; and an exclusive OR circuit which receives an output signal from said OR means and said input signal.

Claim 18

An output circuit for a semiconductor integrated circuit, according to claim 8 wherein said control means includes: a first means which receives said input signal, and provides an output signal to said first and second switching means when said first control signal is in said first state; an exclusive OR means which receives said input signal and said second control signal; and a second means which receives an output signal from said exclusive OR means, and provides an output signal to said first and second switching means when said first control signal is in said second state.