Noise control in an integrated circuit chip

Claim 1

An integrated circuit construction and arrangement, comprising logic means integrated into a semiconductor substrate, a plurality of N of groups of switchable driver circuit means integrated into said semiconductor substrate, each group of driver circuit means including a plurality of individual driver circuits, each individual driver circuit having a switching signal input means, an enable signal input means, and an output signal means, means connecting the switching signal input means of each of said individual driver circuits to said logic means, a source of enable signals operable to provide a like plurality N of enable signals, each individual enable signal of which occurs at a different time, means connecting a different one of said enable signals to a different one of said N groups of driver circuit means and to the driver enable signal input means of each individual driver circuit in the group, to thereby inhibit an overlap in switching activity of the output signal means of said plurality N of driver circuit means, a second logic means having clocked receiver circuits connected to said output signal means and having repeating machine cycles, wherein the state of said logic means is to be interrogate in at least one of said machine cycles, and wherein said plurality N of enable signals are repeated in each cycle in which the state of said logic means is to be interrogated, and said plurality N of driver circuit means groups being physically grouped on said substrate such that a driver circuit means group that is active during a given portion of said at least one machine cycle is physically separated from the driver circuit means groups that are to be stable during said given portion of said at least one machine cycle.