Patent US5283449A successfully refreshed from Google Patents.
US5283449A
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US
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Semiconductor integrated circuit device including two types of MOSFETS having source/drain region different in sheet resistance from each other
Assignee: Renesas Electronics Corp
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Filing: 1991-08-08
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Granted: 1994-02-01
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Expires: 2011-08-08
Abstract
Abstract In the semiconductor integrated circuit device of the present invention which uses MOSFETs as its components, the gate electrode of the MOSFET is constructed by using a silicide gate, a polycide gate or a metal gate. The source-drain region of the MOSFET for the internal circuit which does not require connection to an external circuit has a silicide structure, and the source-drain region of the MOSFET for the buffer circuit which requires a direct connection to an external device has a region which is not of silicide structure at least in a portion adjacent to the gate electrode. The gate electrode and the source-drain region of the internal circuit have low resistances so that it is possible to realize an increase in the operating speed by using them as a part of the wirings. Further, in the source-drain region of the buffer circuit there is provided a region of high resistance in the vicinity of the gate electrode so that it is possible to enhance the ESD resistance.
Inventors
- 👤 Hideyuki Ooka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:57
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/811; H10D30/00; H10D30/60; H10D62/00; H10D62/80; H10D62/83; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/60; H10D64/62; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/44; H10W20/4403; H10W20/4437; H10W20/4441
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
208 words
A semiconductor integrated circuit device, comprising: a buffer circuit including a first MOSFET to interface with an external device and an internal circuit operatively coupled to said buffer circuit and including a second MOSFET, said first MOSFET having a first gate electrode formed on a first insulating film covering a first channel region, a first source region and a first drain region, each of said first source and first drain regions having a first end portion defining said first channel region, said second MOSFET having a second gate electrode formed on a second insulating film covering a second channel region, a second source region and a second drain region, each of said second source and second drain regions having a second end portion defining said second channel region, said first MOSFET further having a first silicide film selectively formed on a surface of at least one of said first source and first drain regions at a first distance from said first end portion, and said second MOSFET further having a second silicide film selectively formed on a surface of at least one of said second source and second drain regions at a second distance from said second end portion, said first distance being larger than said second distance.
Claim 2
Dependent Claim
208 words
A semiconductor integrated circuit device, comprising: a buffer circuit including a first MOSFET to interface with an external device and an internal circuit operatively coupled to said buffer circuit and including a second MOSFET, said first MOSFET having a first gate electrode formed on a first insulating film covering a first channel region, a first source region and a first drain region, each of said first source and first drain regions having a first end portion defining said first channel region, said second MOSFET having a second gate electrode formed on a second insulating film covering a second channel region, a second source region and a second drain region, each of said second source and second drain regions having a second end portion defining said second channel region, said first MOSFET further having a first silicide film selectively formed on a surface of at least one of said first source and first drain regions at a first distance from said first end portion, and said second MOSFET further having a second silicide film selectively formed on a surface of at least one of said second source and second drain regions at a second distance from said second end portion, said first distance being larger than said second distance.
Claim 3
Dependent Claim
45 words
The semiconductor integrated circuit device as claimed in claim 1, wherein each of said first and second gate electrodes includes a third silicide film of a first metal and each of said first and second silicide films is made of silicon and a second metal.
Claim 4
Dependent Claim
32 words
The semiconductor integrated circuit device as claimed in claim 2, wherein said first metal is selected from tungsten, molybdenum and titanium and said second metal is selected from titanium, cobalt and tantalum.
Claim 5
Dependent Claim
131 words
A semiconductor integrated circuit device, comprising: a buffer circuit including a first MOSFET to interface with an external device and an internal circuit operatively coupled to said buffer circuit and including a second MOSFET, each of said first and second MOSFETs having a gate electrode and source and drain regions, said second MOSFET further having a silicide film formed on the surface of at least one of said source and drain regions thereof, wherein said first MOSFET has no silicide film in contact with said source and drain regions thereof to increase the resistance of said source and drain regions of said first MOSFET to be greater than the resistance of said at least one of said source and drain regions of said second MOSFET having formed thereon said silicide film.
Claim 6
Dependent Claim
131 words
A semiconductor integrated circuit device, comprising: a buffer circuit including a first MOSFET to interface with an external device and an internal circuit operatively coupled to said buffer circuit and including a second MOSFET, each of said first and second MOSFETs having a gate electrode and source and drain regions, said second MOSFET further having a silicide film formed on the surface of at least one of said source and drain regions thereof, wherein said first MOSFET has no silicide film in contact with said source and drain regions thereof to increase the resistance of said source and drain regions of said first MOSFET to be greater than the resistance of said at least one of said source and drain regions of said second MOSFET having formed thereon said silicide film.
Claim 7
Dependent Claim
54 words
The semiconductor integrated circuit device as claimed in claim 4, wherein each said gate electrode includes a silicide film of a first metal and said silicide film formed on the surface of said at least one of said source and drain regions of said second MOSFET is made of silicon and a second metal.
Claim 8
Dependent Claim
32 words
The semiconductor integrated circuit device as claimed in claim 5, wherein said first metal is selected from tungsten, molybdenum and titanium and said second metal is selected from titanium, cobalt and tantalum.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-31 | 1997-08-02 | 1998-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-31 | 2001-08-02 | 2002-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-31 | 2005-08-02 | 2006-02-01 | $7700.00 | Window Closed / Lapsed |