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US5282162A
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Semiconductor memory device having capacitor of thin film transistor structure
Assignee: Toshiba Corp
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Filing: 1991-05-23
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Granted: 1994-01-25
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Expires: 2011-05-23
Abstract
Abstract The gate of a transistor Q1 serving as a selection transistor is connected to a word line and the source thereof is connected to a bit line BL. The gate of a transistor Q2 serving as a cell capacitor is connected to the drain of the transistor Q1 and the drain thereof is connected to a pulse generation circuit. Whether an inverted layer is formed in the channel region of the transistor Q2 or not is determined according to the stored data. An inverted layer is formed in the channel region of the transistor Q2 having data "1" stored as storage data. The source of the transistor Q2 is connected to the gate of a transistor Q3. The drain of the transistor Q3 is connected to a pulse generation circuit 11 and the source thereof is connected to the drain of the transistor Q1. The transistor Q2 having an inverted layer formed therein is turned on when a preset voltage is supplied from the pulse generation circuit 11 in the stored data reading operation, and in this case, the transistor Q3 is turned on. Therefore, a current can be supplied to the bit line BL from the pulse generation circuit 11 via the transistor Q3 and the selected transistor Q1.
Inventors
- 👤 Kiyofumi Ochii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 22:32
CPC Classifications
H; H10; H10B; H10B12/00; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G11C11/403; G11C11/405; G11C8/00; G11C8/08; G11C8/14
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
155 words
A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a first transistor having a gate coupled to the word line and a current path having a first end coupled to the bit line, and a second end; a second transistor for storing data, including a control input coupled to the second end of said first transistor, and a current path having first and second ends; pulse generation means for supplying a voltage pulse to the first end of the current path of said second transistor during a readout of stored data; and a third transistor including a control input coupled to the second end of the current path of said second transistor such as to be responsive to a conduction state of said second transistor, and a current path coupled between said pulse generation means and the second end of the current path of the first transistor.
Claim 2
Dependent Claim
155 words
A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a first transistor having a gate coupled to the word line and a current path having a first end coupled to the bit line, and a second end; a second transistor for storing data, including a control input coupled to the second end of said first transistor, and a current path having first and second ends; pulse generation means for supplying a voltage pulse to the first end of the current path of said second transistor during a readout of stored data; and a third transistor including a control input coupled to the second end of the current path of said second transistor such as to be responsive to a conduction state of said second transistor, and a current path coupled between said pulse generation means and the second end of the current path of the first transistor.
Claim 3
Dependent Claim
33 words
A device according to claim 1, wherein said second and third transistors include a thin film structure and said third transistor has a gate electrode including a channel region of said second transistor.
Claim 4
Dependent Claim
32 words
A device according to claim 1, wherein said second and third transistors include polysilicon and the impurity concentration of the channel regions thereof is lower than that of respective remaining portions thereof.
Claim 5
Dependent Claim
82 words
A device according to claim 1, wherein said pulse generation means includes an oscillation circuit for generating a pulse signal; a booster circuit for raising a pulse signal generated from said oscillation circuit to a preset potential; and a supply circuit for supplying the preset potential from said booster circuit to said second transistor before said first transistor is selected during the readout of stored data and interrupting supply of the potential to said second transistor while said first transistor is selected.
Claim 6
Dependent Claim
157 words
A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a first transistor having a gate coupled to the word line and a current path having a first end coupled to the bit line, and a second end; a second transistor for storing data, including a gate coupled to the second end of said first transistor, and a current path having a first end and a second end; pulse generation means coupled to the first end of the current path of said second transistor, for supplying a voltage pulse to said second transistor during a readout of stored data; and a third transistor having a gate coupled to the second end of the current path of said second transistor, and a current path having a first end coupled to the second end of the current path of said first transistor and a second end coupled to said pulse generation means.
Claim 7
Dependent Claim
157 words
A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a first transistor having a gate coupled to the word line and a current path having a first end coupled to the bit line, and a second end; a second transistor for storing data, including a gate coupled to the second end of said first transistor, and a current path having a first end and a second end; pulse generation means coupled to the first end of the current path of said second transistor, for supplying a voltage pulse to said second transistor during a readout of stored data; and a third transistor having a gate coupled to the second end of the current path of said second transistor, and a current path having a first end coupled to the second end of the current path of said first transistor and a second end coupled to said pulse generation means.
Claim 8
Dependent Claim
33 words
A device according to claim 5, wherein said second and third transistors include a thin film structure and said third transistor has a gate electrode including a channel region of said second transistor.
Claim 9
Dependent Claim
33 words
A device according to claim 5, wherein said second and third transistors include polysilicon and the impurity concentration of the channel regions thereof is lower than that of the respective remaining portions thereof.
Claim 10
Dependent Claim
82 words
A device according to claim 5, wherein said pulse generation means includes an oscillation circuit for generating a pulse signal; a booster circuit for raising a pulse signal generated from said oscillation circuit to a preset potential; and a supply circuit for supplying the preset potential from said booster circuit to said second transistor before said first transistor is selected during the readout of stored data and interrupting supply of the potential to said second transistor while said first transistor is selected.
Claim 11
Dependent Claim
179 words
A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a first transistor having a gate coupled to the word line and a current path having a first end coupled to the bit line, and a second end; a second transistor for storing data, including a control input coupled to the second end of said first transistor, and a current path having first and second ends; pulse generation means for supplying a voltage pulse to the first end of the current path of said second transistor during a readout of stored data; a third transistor including a control input coupled to the second end of the current path of said second transistor such as to be responsive to a conduction state of said second transistor, and a current path coupled between said pulse generation means and the second end of the current path of the first transistor; and supplying means for supplying a pulse signal from said pulse generation means to said second and third transistors in response to a selection signal.
Claim 12
Dependent Claim
179 words
A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a first transistor having a gate coupled to the word line and a current path having a first end coupled to the bit line, and a second end; a second transistor for storing data, including a control input coupled to the second end of said first transistor, and a current path having first and second ends; pulse generation means for supplying a voltage pulse to the first end of the current path of said second transistor during a readout of stored data; a third transistor including a control input coupled to the second end of the current path of said second transistor such as to be responsive to a conduction state of said second transistor, and a current path coupled between said pulse generation means and the second end of the current path of the first transistor; and supplying means for supplying a pulse signal from said pulse generation means to said second and third transistors in response to a selection signal.
Claim 13
Dependent Claim
14 words
A device according to claim 9, wherein said supplying means includes an AND circuit.
Claim 14
Dependent Claim
183 words
A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a first transistor having a gate coupled to the word line, and a first current path having a first end coupled to the bit line and a second end; a second transistor having a gate coupled to the second end of the current path of the first transistor, and a second current path having a first end and a second end, said gate serving as a storage node for storing data, and said second current path being conductive when the data is stored in said gate; pulse generation means for generating a pulse signal, and for supplying the pulse signal to the first end of the second current path during a readout of the stored data; and a third transistor including a gate coupled to the second end of the second current path such as to be responsive to a conduction state of said second transistor, and a third current path coupled between said pulse generation means and the second end of the first current path.
Claim 15
Dependent Claim
183 words
A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a first transistor having a gate coupled to the word line, and a first current path having a first end coupled to the bit line and a second end; a second transistor having a gate coupled to the second end of the current path of the first transistor, and a second current path having a first end and a second end, said gate serving as a storage node for storing data, and said second current path being conductive when the data is stored in said gate; pulse generation means for generating a pulse signal, and for supplying the pulse signal to the first end of the second current path during a readout of the stored data; and a third transistor including a gate coupled to the second end of the second current path such as to be responsive to a conduction state of said second transistor, and a third current path coupled between said pulse generation means and the second end of the first current path.
References Cited (Backward Citations)
US3706079A
Cited
US4592020A
Cited
US4545034A
Cited
US4633438A
Cited
US4786954A
Cited
US4669062A
Cited
US4849801A
Cited
US4845673A
Cited
US4855801A
Cited
EP0329569A2
Cited
JPH021155A
Cited
JPH0266967A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-24 | 1997-07-26 | 1998-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-24 | 2001-07-26 | 2002-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-24 | 2005-07-26 | 2006-01-25 | $7700.00 | Window Closed / Lapsed |