Method and apparatus for optimizing a logic network

Claim 2

A logic synthesis method for optimizing a logic network, comprising the steps of: expressing the logic network as an original graph having a plurality of vertices each representing a set of connections within the logic network which can be simultaneously inverted without modifying the function of the logic network and without increasing the cost of the logic network, a plurality of edges which connect the vertices and which represent connections in the logic network, and inversion markings, disposed on the edges, for representing inverters in the logic network; determining at least one fundamental cycle in the original graph, the at least one fundamental cycle being those vertices and edges of the original graph which form a loop and from which any other loops in the original graph can be derived; sorting the determined at least one fundamental cycle in accordance with a parity of the determined at least one fundamental cycle, the parity being determined in accordance with an odd and even number of inversion markings in the at least one fundamental cycle; forming a final graph by processing the at least one fundamental cycle so as to optimize inverter placement therein while maintaining the parity of the at least one fundamental cycle; comparing the inversion markings of the original and final graphs to determine a set of transformation locations in the logic network; and re-configuring the logic network in accordance with the determined transformation locations.

Claim 3

The method according to claim 1, wherein said determining step includes conducting a depth first search.

Claim 4

The method according to claim 1, wherein said final graph forming step includes removing inversion markings from the graph, thereby forming an inversion-free graph.

Claim 5

The method according to claim 3, wherein an inversion marking is applied to a sorted odd fundamental cycle having a fewest number of vertices.

Claim 6

The method according to claim 3, wherein said final graph forming step further includes applying a fewest number of inversion markings to the edges of the inversion-free graph such that an optimal number of sorted odd fundamental cycles of the tree graph are odd.

Claim 7

The method according to claim 5, wherein said final graph forming step further includes applying a fewest number of inversion markings to the edges of the inversion-free graph such that an optimal number of sorted even fundamental cycles remain even.

Claim 8

The method according to claim 1, further comprises storing information representing edges which are timing critical, and wherein said final graph forming step includes adding inversion markings only on those edges which are not timing critical.

Claim 9

The method according to claim 1, wherein said final graph forming step includes applying a transformation which inverts a connection by adding an inverter to the connection.

Claim 10

The method according to claim 1, wherein said final graph forming step includes applying a transformation which inverts a connection without adding an inverter to the connection.

Claim 11

The method according to claim 1, wherein said expressing step includes applying a transformation which re-configures the logic network such that the reconfigured logic network is of lower cost than the logic network, and includes adding inverters to the reconfigured logic network such that a function of the reconfigured logic network is equal to a function of the logic network.

Claim 12

The method according to claim 1, wherein said re-configuring step further includes designating vertices in accordance with said comparison.

Claim 13

The method according to claim 1, further comprising storing transformations for circuit elements of the logic network, and wherein said re-configuring step includes applying stored transformations to said designated vertices.

Claim 14

The method according to claim 1, further comprising a step of inputting cost information representing a cost of a logic transformation.

Claim 15

The method according to claim 1, wherein one of said vertices is an uninvertible vertex which represents all connections in the logic network which cannot be inverted

Claim 16

A logic synthesizer for optimizing a logic network, comprising: means for expressing the logic network as an original graph having a plurality of vertices each representing a set of connections within the logic network which can be simultaneously inverted without modifying the function of the logic network and without increasing a cost of the logic network, a plurality of edges which connect the vertices and which represent connections in the logic network, and inversion markings, disposed on the edges, for representing inverters in the logic network; means for determining at least one fundamental cycle in the original graph, the at least one fundamental cycle being those vertices and edges of the original graph which form a loop and from which any other loops in the original graph can be derived; means for sorting the determined at least one fundamental cycle in accordance with a parity of the determined at least one fundamental cycle, the parity being determined in accordance with an odd and even number of inversion markings in the at least one fundamental cycle; means for forming a final graph by processing the at least one fundamental cycle so as to optimize inverter placement therein while maintaining the parity of the at least one fundamental cycle; a comparator for comparing the inversion markings of the original and final graphs to determine a set of transformation locations in the logic network; and means for re-configuring the logic network in accordance with the determined transformation locations.

Claim 17

A logic synthesizer for optimizing a logic network, comprising: means for expressing the logic network as an original graph having a plurality of vertices each representing a set of connections within the logic network which can be simultaneously inverted without modifying the function of the logic network and without increasing a cost of the logic network, a plurality of edges which connect the vertices and which represent connections in the logic network, and inversion markings, disposed on the edges, for representing inverters in the logic network; means for determining at least one fundamental cycle in the original graph, the at least one fundamental cycle being those vertices and edges of the original graph which form a loop and from which any other loops in the original graph can be derived; means for sorting the determined at least one fundamental cycle in accordance with a parity of the determined at least one fundamental cycle, the parity being determined in accordance with an odd and even number of inversion markings in the at least one fundamental cycle; means for forming a final graph by processing the at least one fundamental cycle so as to optimize inverter placement therein while maintaining the parity of the at least one fundamental cycle; a comparator for comparing the inversion markings of the original and final graphs to determine a set of transformation locations in the logic network; and means for re-configuring the logic network in accordance with the determined transformation locations.

Claim 18

The logic synthesizer according to claim 15, representing a transformation for at least one of an AND gate, an OR gate, a NOR gate, a NAND gate, an EXCLUSIVE OR gate, an EXCLUSIVE NOR gate, a full adder circuit, a decoder circuit, a multiplexer, a comparator, and a latch circuit.