Alignment of sign, data, edit byte operand results for storage in memory

Claim 2

In a digital computer system having a memory for storing instructions and operands to be operated upon in response to the instructions, processing means responsive to the instructions including an arithmetic processing means, said processing means being responsive to the instructions for performing operations on a number of operands having a plurality of data types to produce a result including a plurality of digits, and bus means for passing instructions and operands among the memory and processing means, the memory being organized as contiguous addressable words, each word comprising a plurality of bytes, each byte organized as two digits, the operands occupying contiguous digit positions or byte positions within a word or over several contiguous words, apparatus being operatively coupled to said memory, to said bus means and to said arithmetic processing means, said apparatus for assembling output operands representative of said digits of said result produced by said arithmetic processing means into a data type specified by instructions for writing into said memory, the apparatus comprising: a number of storage registers coupled to said bus means and to said processing means for storing a number of predetermined constants, a plurality of computed sign bytes, memory retrieved operand bytes and memory retrieved operand decimal digits or bytes, edit character information generated during initial instruction processing, and for storing said result digits; a first register having a plurality of byte positions for providing a capacity equal to that of a memory word; first loading means coupled to said first register for selectively loading said plurality of byte positions of the first register according to said data type; first selection means coupled to said first loading means and to predetermined ones of said storage registers for selecting and providing to the first loading means, data bytes selected from any one of said number of storage registers containing; a plurality of predetermined data bytes corresponding to said edit character information; one of said predetermined constants; said plurality of computed sign bytes; said memory retrieved operand bytes; or memory retrieved operand bytes comprising an operand byte or a decimal byte or two digits; a second register having a plurality of digit positions for providing a capacity equal to that of a memory word; second loading means coupled to said second register for selectively loading said plurality of digit positions of the second register according to said data type; second selection means coupled to said second loading means and to other ones of said plurality of storage registers for selecting and providing to the second loading means, all result digits selected from any one of said other ones of said plurality of storage registers containing; said memory retrieved operand digits; or said result digits produced by said arithmetic processing means in response to the instructions, and OR means for producing an output word of said number of input operands in said data type which is the logical OR of the first register byte contents and the second register digit contents for writing into memory.

Claim 3

The digital computer system of claim 1, wherein the memory in response to a write mask constant, having as many bit positions as there are bytes in a memory word, stores only those byte positions of a word corresponding to a first state of a corresponding bit of the write mask constant and leaves undisturbed, those byte positions of a word corresponding to a second state opposite to the first state of a corresponding bit of the write mask and wherein each apparatus further comprises: register means connected to receiving said write mask constant for providing said write mask constant to the memory, said register means being connected to be loaded with bits of said first state designating all valid byte positions of the output word produced by said OR means which correspond to valid data loaded by the first or second loading means.

Claim 4

In a digital computer system having a memory for storing instructions and operands to be operated upon in response to the instructions, processing means responsive to the instructions including an arithmetic processing means, said processing means being responsive to the instructions for performing operations on a number of operands having a plurality of data types to produce a result including a plurality of digits, and bus means for passing instructions and operands among the memory and processing means, and the memory being organized as contiguous addressable words, each word comprising a plurality of bytes, each byte organized as two digits, the operands occupying contiguous digit positions or byte positions within a word or over several contiguous words, apparatus being operatively coupled to said memory, to said bus means and to said arithmetic processing means, said apparatus for assembling output operands corresponding to said digits of said result into a data type specified by one of said instructions for writing into said memory, the apparatus comprising: a number of storage registers coupled to said bus means for storing a number of predetermined constants, computed sign bytes, memory retrieval operand bytes and digits, edit character information generated during initial instruction processing, and for storing said result digits; a first register having a plurality of bytes positions for providing a capacity equal to that of a memory word; first loading means coupled to said first register for selectively loading said byte positions of the first register according to said data type; first selection means coupled to said first loading means and to predetermined ones of said storage registers for selecting and providing to the first loading means in response to said instruction, data bytes selected from any one of said registers containing: a plurality of predetermined data bytes corresponding to said edit character information; one of said number of said predetermined constants; a plurality of computed sign bytes; memory retrieved operand bytes; memory retrieved operand bytes comprising an operand byte or decimal byte or two four-bit digits; or memory retrieved digits corresponding to operand bytes, each comprising a predetermined four-bit sign field and four data bits; a second register having a plurality of digit position for providing a capacity equal to that of a memory word; second loading means coupled to said second register for selectively loading digit positions of the second register according to said data type; second selection means coupled to said second loading means and to other ones of said plurality of storage registers for selecting and providing to the second loading means in response to said instruction, all of said plurality of digits of said result selected from any one of said other registers containing: memory retrieved operand word digits; or result digits produced by said arithmetic processor means in response to the instructions, and third selection means coupled to said second register for selecting as a word either the digit contents of the second register or alternating ZERO digits and selected digits of the second register; and, OR means for producing an output word in said data type which is the logical OR of the first register byte contents and the output of the third selection means for writing into memory.

Claim 5

In a digital computer system having a memory for storing instructions and operands to be operated upon in response to the instructions, processing means responsive to the instructions including an arithmetic processing means, said processing means being responsive to the instructions for performing operations on a number of operands having a plurality of data types to produce a result including a plurality of digits, and bus means for passing instructions and operands among the memory and processing means, and the memory being organized as contiguous addressable words, each word comprising a plurality of bytes, each byte organized as two digits, the operands occupying contiguous digit positions or byte positions within a word or over several contiguous words, apparatus being operatively coupled to said memory, to said bus means and to said arithmetic processing means, said apparatus for assembling output operands corresponding to said digits of said result into a data type specified by one of said instructions for writing into said memory, the apparatus comprising: a number of storage registers coupled to said bus means for storing a number of predetermined constants, computed sign bytes, memory retrieval operand bytes and digits, edit character information generated during initial instruction processing, and for storing said result digits; a first register having a plurality of bytes positions for providing a capacity equal to that of a memory word; first loading means coupled to said first register for selectively loading said byte positions of the first register according to said data type; first selection means coupled to said first loading means and to predetermined ones of said storage registers for selecting and providing to the first loading means in response to said instruction, data bytes selected from any one of said registers containing: a plurality of predetermined data bytes corresponding to said edit character information; one of said number of said predetermined constants; a plurality of computed sign bytes; memory retrieved operand bytes; memory retrieved operand bytes comprising an operand byte or decimal byte or two four-bit digits; or memory retrieved digits corresponding to operand bytes, each comprising a predetermined four-bit sign field and four data bits; a second register having a plurality of digit position for providing a capacity equal to that of a memory word; second loading means coupled to said second register for selectively loading digit positions of the second register according to said data type; second selection means coupled to said second loading means and to other ones of said plurality of storage registers for selecting and providing to the second loading means in response to said instruction, all of said plurality of digits of said result selected from any one of said other registers containing: memory retrieved operand word digits; or result digits produced by said arithmetic processor means in response to the instructions, and third selection means coupled to said second register for selecting as a word either the digit contents of the second register or alternating ZERO digits and selected digits of the second register; and, OR means for producing an output word in said data type which is the logical OR of the first register byte contents and the output of the third selection means for writing into memory.

Claim 6

The digital computer system of claim 3, wherein the memory in response to a write mask constant having as many bit positions as there are bytes in a memory word stores only those byte positions of a word corresponding to a first state of a corresponding bit of the write mask constant and leaves undisturbed those byte positions of a word corresponding to a second state opposite to the first state of a corresponding bit of the write mask and wherein said apparatus further comprises: register means connected to said processing means for receiving said write mask constant for providing a write mask to the memory, said register means being connected to be loaded with bits of said first state designating all valid byte positions of the output word produced by said OR means which correspond to those byte positions loaded with valid data by the first or second loading means.