Patent US5270584A successfully refreshed from Google Patents.
US5270584A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit
Assignee: Renesas Electronics Corp
•
Filing: 1992-08-26
•
Granted: 1993-12-14
•
Expires: 2012-08-26
Abstract
Abstract A semiconductor integrated circuit which comprises a detection circuit for detecting a voltage of a semiconductor substrate and a negative voltage generating circuit for generating a negative voltage to be supplied to the substrate in accordance with an output signal of the detection circuit. The detection circuit includes a first P-channel MOS transistor having a gate connected to a ground potential, a source connected to a power source and a drain connected to a node coupled to the detection circuit, and a second P-channel MOS transistor having a gate connected to the substrate, a source connected to the node and a drain connected to ground. Current does not flow from the external power source to the substrate, so that, even if the negative voltage generating circuit does not have its electric current supplying capacity increased, the voltage of the substrate can be detected. A buffer circuit outputting a signal in accordance with the node voltage level, and ring oscillators switched in accordance with the signal of the buffer circuit may be used in supplying an electric current to the negative voltage generating circuit.
Inventors
- 👤 Yasuji Koshikawa
- 👤 Tadahiko Sugibayashi
- 👤 Takahiro Hara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:04
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/145; G11C5/146
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
125 words
A semiconductor integrated circuit comprising: a detection circuit for detecting a voltage of a semiconductor substrate; and a negative voltage generating circuit for generating a negative voltage to be supplied to said substrate in accordance with the output signal from said detection circuit; said detection circuit including a first P-channel MOS transistor having the gate connected to a ground potential end, the source connected to a power source terminal for receiving a power source voltage from an external power source and the drain connected to a node to be supplied with an output of said detection ciuduit, and a second P-channel MOS transistor having the gate connected to said substrate, the source connected to said node and the drain connected to said ground potential end.
Claim 2
Dependent Claim
125 words
A semiconductor integrated circuit comprising: a detection circuit for detecting a voltage of a semiconductor substrate; and a negative voltage generating circuit for generating a negative voltage to be supplied to said substrate in accordance with the output signal from said detection circuit; said detection circuit including a first P-channel MOS transistor having the gate connected to a ground potential end, the source connected to a power source terminal for receiving a power source voltage from an external power source and the drain connected to a node to be supplied with an output of said detection ciuduit, and a second P-channel MOS transistor having the gate connected to said substrate, the source connected to said node and the drain connected to said ground potential end.
Claim 3
Dependent Claim
69 words
A semiconductor integrated circuit as claimed in claim 1 comprising a buffer circuit for outputting a signal having a first and second logical state in accordance with a voltage level of said node, and a plurality of ring oscillators which are to be switched in accordance with the logical state of the output signal of said buffer circuit thereby supplying an electric current to said negative voltage generating circuit.
Claim 4
Dependent Claim
27 words
A semiconductor integrated circuit as claimed in claim 2, wherein said buffer circuit has a logical gate including of P-channel MOS transistors at a first stage thereof.
Claim 5
Dependent Claim
17 words
A semiconductor integrated circuit as claimed in claim 3, wherein said logical gate includes a PMOS inverter.
Claim 6
Dependent Claim
119 words
A semiconductor integrated circuit comprising: a detection circuit for detecting a voltage of a semiconductor substrate; and a negative voltage generating circuit for generating a negative voltage to be supplied to said substrate in accordance with the output signal from said detection circuit; said detection circuit including a first P-channel MOS transistor having the gate connected to a ground potential end, the source connected to a reference voltage terminal for receiving a reference voltage, and the drain connected to a node to be supplied with an output of said detection circuit, and a second P-channel MOS transistor having the gate connected to said substrate, the source connected to said node and the drain connected to said ground potential end.
Claim 7
Dependent Claim
119 words
A semiconductor integrated circuit comprising: a detection circuit for detecting a voltage of a semiconductor substrate; and a negative voltage generating circuit for generating a negative voltage to be supplied to said substrate in accordance with the output signal from said detection circuit; said detection circuit including a first P-channel MOS transistor having the gate connected to a ground potential end, the source connected to a reference voltage terminal for receiving a reference voltage, and the drain connected to a node to be supplied with an output of said detection circuit, and a second P-channel MOS transistor having the gate connected to said substrate, the source connected to said node and the drain connected to said ground potential end.
Claim 8
Dependent Claim
69 words
A semiconductor integrated circuit as claimed in claim 5 comprising a buffer circuit for outputting a signal having a first and second logical state in accordance with a voltage level of said node, and a plurality of ring oscillators which are to be switched in accordance with the logical state of the output signal of said buffer circuit thereby supplying an electric current to said negative voltage generating circuit.
Claim 9
Dependent Claim
26 words
A semiconductor integrated circuit as claimed in claim 6, wherein said buffer circuit has a logical gate including P-channel MOS transistors at a first stage thereof.
Claim 10
Dependent Claim
24 words
A semiconductor integrated circuit as claimed in claim 6, wherein said buffer circuit is supplied with a reference voltage from said reference voltage terminal.
Claim 11
Dependent Claim
17 words
A semiconductor integrated circuit as claimed in claim 7, wherein said logical gate includes a PMOS inverter.
References Cited (Backward Citations)
US4455493A
Cited
US4700125A
Cited
US4871927A
Cited
US4948995A
Cited
US4933627A
Cited
US5113088A
Cited
US5120993A
Cited
US5157287A
Cited
US5191235A
Cited
US5179296A
Cited
US5168174A
Cited
US5153465A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-13 | 1997-06-14 | 1997-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-13 | 2001-06-14 | 2001-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-13 | 2005-06-14 | 2005-12-14 | $7700.00 | Window Closed / Lapsed |