Disenabling circuit for power-on event

Claim 1

A disenabling circuit operative to cause component circuits to shift into respective disenabling states for a predetermined time period after a power-on event, comprising: (a) a level detecting circuit provided with a series combination of plural load transistors of one channel conductivity type and at least one shifting transistor of the opposite channel conducitivity type coupled between a power supplying line and a source of constant voltage, an output node thereof being provided between said plural load transistors and said shifting transistor; and (b) a complementary inverter circuit coupled at an input node thereof to the output node of said level detecting circuit and having an output node where a disenabling signal is produced, wherein said shifting transistor is responsive to the voltage level at the output node of said complementary inverter circuit, and wherein said shifting transistor has a gate electrode directly coupled to the output node of said complementary inverter circuits and one of said load transistors has a gate electrode coupled to said constant source of voltage and in which the other load transistors have respective gate electrodes couples to respective drain nodes thereof.