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Ratioed power on reset circuit

Assignee: United States Department of the Air Force
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Filing: 1987-01-14
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Granted: 1988-07-05
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Expires: 2007-01-14
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Abstract

Abstract A ratioed power on reset apparatus utilizing two pairs of field effect transistors as voltage dividers to generate a power on reset signal which tracks the waveshape of an applied power signal with a slot rise time.

Inventors

  • 👤 Douglas S. Piasecki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 03:46
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K17/223

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 452 words
A ratioed power reset apparatus comprising in combination: a source providing a power supply signal which upon initial application increases from zero volts to some predetermined constant value, said power supply signal being applied to a power bus and referenced to ground, a first control circuit comprising a first means for dividing voltage and a first means for controlling, said first voltage dividing means connected in series to said first controlling means, said first control circuit connected between said power bus and ground, a second control circuit comprising a second means for dividing voltage and a second means for controlling, said second voltage dividing means connected in series to said second controlling means, said second control circuit connected between said power bus and ground, a third control circuit comprising a third and fourth means for controlling, said third and fourth controlling means connected in series, said third and fourth controlling means comprising complementary semiconductor devices, said third third control circuit connected between said power bus and ground, said third and fourth controlling means providing an output at their common connection, a first means for inverting connected to receive said output from said third control circuit, and first inverting means having an input and an output, a second means for inverting, said second inverting means having an input and an output, said input of said second inverting means connected to said output of said first inverting means, said first voltage dividing means having a first and second input and an output, said output of said first inverting means connected to said first input of said first voltage dividing means, said second input of said first voltage dividing means connected to ground, said first controlling means having an input, said input of said first controlling means connected to said power bus, said output of said first voltage dividing means connected to the input of said second controlling means, said second voltage dividing means having a first and second input and an output, said first input of said second voltage dividing means connected to said power bus, said second input of said second voltage dividing means connected to said output of said second inverter means, said third and fourth controlling means respectively having an input, said inputs of said third and fourth controlling means connected together and to said output of said second voltage dividing means, so that as said power supply signal increases in amplitude towards its final value, a power on reset signal is generated at said output of said second inverter means, said power on reset signal tracks said power supply signal until said final value is reached and then said power on reset set signal abruptly changes to approximately zero volts.
Claim 2
Dependent Claim 452 words
A ratioed power reset apparatus comprising in combination: a source providing a power supply signal which upon initial application increases from zero volts to some predetermined constant value, said power supply signal being applied to a power bus and referenced to ground, a first control circuit comprising a first means for dividing voltage and a first means for controlling, said first voltage dividing means connected in series to said first controlling means, said first control circuit connected between said power bus and ground, a second control circuit comprising a second means for dividing voltage and a second means for controlling, said second voltage dividing means connected in series to said second controlling means, said second control circuit connected between said power bus and ground, a third control circuit comprising a third and fourth means for controlling, said third and fourth controlling means connected in series, said third and fourth controlling means comprising complementary semiconductor devices, said third third control circuit connected between said power bus and ground, said third and fourth controlling means providing an output at their common connection, a first means for inverting connected to receive said output from said third control circuit, and first inverting means having an input and an output, a second means for inverting, said second inverting means having an input and an output, said input of said second inverting means connected to said output of said first inverting means, said first voltage dividing means having a first and second input and an output, said output of said first inverting means connected to said first input of said first voltage dividing means, said second input of said first voltage dividing means connected to ground, said first controlling means having an input, said input of said first controlling means connected to said power bus, said output of said first voltage dividing means connected to the input of said second controlling means, said second voltage dividing means having a first and second input and an output, said first input of said second voltage dividing means connected to said power bus, said second input of said second voltage dividing means connected to said output of said second inverter means, said third and fourth controlling means respectively having an input, said inputs of said third and fourth controlling means connected together and to said output of said second voltage dividing means, so that as said power supply signal increases in amplitude towards its final value, a power on reset signal is generated at said output of said second inverter means, said power on reset signal tracks said power supply signal until said final value is reached and then said power on reset set signal abruptly changes to approximately zero volts.
Claim 3
Dependent Claim 38 words
A ratioed power reset apparatus as described in claim 1 wherein said first voltage dividing means comprises a pair of p-channel field effect transistors connected in series and said first control means comprises an n-channel field effect transistor.
Claim 4
Dependent Claim 38 words
A ratioed power reset apparatus as described in claim 1 wherein said second voltage dividing means comprises a pair of n-channel field effect transistors connected in series and said second control means comprises a p-channel field effect transistor.
Claim 5
Dependent Claim 32 words
A ratioed power reset apparatus as described in claim 1 wherein said third control means is a p-channel field effect transistor and said fourth control means is an n-channel field effect transistor.

References Cited (Backward Citations)

US3628070A Cited
US3753011A Cited
US3809926A Cited
US3895239A Cited
US3950654A Cited
US4196362A Cited
US4385245A Cited
US4553054A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-07-05 1992-01-04 1992-07-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-07-05 1996-01-04 1996-07-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-07-05 2000-01-04 2000-07-05 $7700.00 Window Closed / Lapsed

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