Latch-up prevention in a two-power-supply CMOS integrated circuit by means of a single integrated MOS transistor

Claim 1

A two-power-supply CMOS integrated circuit having a positive, a negative and a ground supply rails and a well region of a first polarity; MOS transistors having a channel of a second polarity being formed within said well region and complementary MOS transistors having a channel of said first polarity being formed outside said well region; the integrated circuit having means for preventing latch-up when said well region is accidentally floated comprising at least an integrated MOS transistor having a channel of said second polarity and having a source, a drain and a body region and a gate terminal; said drain and said body regions being electrically connected in common with said gate terminal to the supply rail of said second polarity and said source region being electrically connected to ground; said integrated transistor being in a turn-off condition under correct supply conditions and functioning in a turn-on saturated condition when limiting the potential excursion of an accidentally floated well region.