US4491746A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-substrate-bias circuit device
Assignee: Toshiba Corp
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Filing: 1981-09-21
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Granted: 1985-01-01
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Expires: 2001-09-21
Abstract
Abstract A self-substrate-bias circuit device comprising substrate of P conductivity type, a capacitor element of MOS construction formed in said semiconductor substrate and whose one end is connected to the output terminal of a pulse generator, a diode element formed in said semiconductor substrate and connected between the other end of said capacitor element and a ground potential, and an P + region of P conductivity type formed in the region of said seminconductor substrate which is contacted to said capacitor element and having higher impurity concentration than that of said semiconductor substrate.
Inventors
- 👤 Hideharu Koike
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:09
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/211; H10D89/213; H10D89/215; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
114 words
A self-substrate-bias circuit device for use with a pulse generator comprising: a semiconductor substrate of a given conductivity type; a capacitor element of MOS construction formed in said semiconductor substrate having a first side connected to the output terminal of the pulse generator; a first diode formed in said semiconductor substrate and connected between the other side of said capacitor element and a reference potential; and a region of said conductivity type formed in a portion of said semiconductor substrate which is contacted to and surrounding said capacitor element and having higher impurity concentration than that of said semiconductor substrate so that carriers from said capacitor element recombine with carriers existing in said region.
Claim 2
Dependent Claim
114 words
A self-substrate-bias circuit device for use with a pulse generator comprising: a semiconductor substrate of a given conductivity type; a capacitor element of MOS construction formed in said semiconductor substrate having a first side connected to the output terminal of the pulse generator; a first diode formed in said semiconductor substrate and connected between the other side of said capacitor element and a reference potential; and a region of said conductivity type formed in a portion of said semiconductor substrate which is contacted to and surrounding said capacitor element and having higher impurity concentration than that of said semiconductor substrate so that carriers from said capacitor element recombine with carriers existing in said region.
Claim 3
Dependent Claim
26 words
A self-substrate-bias circuit device according to claim 1 further including a second diode formed between the other side of said capacitor element and said semiconductor substrate.
Claim 4
Dependent Claim
18 words
A self-substrate-bias circuit device according to claim 1 or 2 wherein said capacitor element is of N-channel type.
Claim 5
Dependent Claim
18 words
A self-substrate-bias circuit device according to claim 1 or 2 wherein said capacitor element is of P-channel type.
Claim 6
Dependent Claim
18 words
A self-substrate-bias circuit device according to claim 1 or 2 wherein said first and second diodes are MOS-constructed.
Claim 7
Dependent Claim
18 words
A self-substrate-bias circuit device according to claim 5 wherein said first and second diodes are of N-channel type.
Claim 8
Dependent Claim
18 words
A self-substrate-bias circuit device according to claim 5 wherein said first and second diodes are of P-channel type.
Claim 9
Dependent Claim
16 words
A self-substrate-bias circuit device according to claim 1 wherein said reference potential is a ground potential.
Claim 10
Dependent Claim
22 words
A self-substrate-bias circuit device according to claim 2 wherein said region is formed to surround said capacitor element and said two diodes.
Claim 11
Dependent Claim
49 words
A self-substrate-bias circuit device according to claim 2 wherein each of said diodes has an anode and a cathode section separated by a region which is of said given conductivity type and has an impurity concentration lower than that of said region contacted to and surrounding said capacitor element.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-01 | 1988-07-02 | 1989-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-01 | 1992-07-02 | 1993-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-01 | 1996-07-02 | 1997-01-01 | $7700.00 | Window Closed / Lapsed |