Processor system with improved memory transfer means

Claim 1

A processor system enabling the transfer of data from a first location in a memory to a second location in said memory in a system which has plural processors and other elements which may request data transfer comprising: a plurality of processors, each of which is coupled to a system memory which has physical storage which may be assigned to main and expanded memory and which provides arrays of memory locations in memory between which locations data may be transfered by a request from a processor or other elements of the system; by data transfer means for transferring data between locations of the memory; said data transfer means including: a processor for selectively generating a data transfer request signal for moving data from a first location in memory to a second location in memory without caching it; a store-in cache connected between said processor and said memory for caching data under processor direction and for providing a mechanism for transfer of data from the processor to memory with a control circuitry; said control circuitry being responsive to said data transfer request signal, said data transfer request control circuitry functioning as a data switch for routing said data through said data transfer buffer in response to said signal, while said control circuitry inhibits routing of data through said store-in cache in response to said data transfer request signal, said control circuitry including, a data switch coupled to said memory for transfering data from memory arrays in said memory through said control circuitry; a data transfer buffer connected to said data switch and to said store-in cache for holding Least Recently Used (LRU) castouts and Cross Interrogate (XI) Castouts; system controls coupled to said data switch for coordinating the data transfer; system priority logic coupled to said data switch and to said system controls for prioritizing requests for transfer from the processor and any other elements of the system; storage protect logic; and cross interogate (XI) logic including stack registers for determining whether a most recent level of data resides in the system storage or in store-in cache; said cross-interrogate logic being coupled to said store-in cache and to said system priority logic and said system controls; said cross interrogate logic including means for locking out new castout requests until a selective requested data transfer is complete.