Sequence control apparatus for producing output signals in synchronous with a consistent delay from rising or falling edge of clock input signal

Claim 2

Sequence control apparatus for providing a plurality of output signals selectively based upon either a rising edge of a clock signal or a falling edge of a clock signal, comprising: clock input signal means; clock input signal inverter means having an input coupled to the clock input signal means and an output; state controller means comprising a first plurality of devices clocked by said clock input signal means and a second plurality of devices clocked by signals from the output of said clock signal inverter means and which can produce a plurality of output signals; means to initiate operations of said state controller means; gating means coupled to said state controller means to receive a plurality of said output signals from said state controller means and having output means on which appears an output signal for the sequence control apparatus; logic select input means coupled to said gating means for selecting a desired one of the output signals from said state controller means to appear on the output means of the gating means; second state controller means comprising a first plurality of devices clocked by said clock input signal means and a second plurality of devices clocked by signals from the output of said clock signal inverter means, and which can produce a plurality of output signals; means for coupling the output means of said gating means to said second state controller means to perform operation thereof; second gating means coupled to said second state controller means to receive a plurality of said output signals from said second state controller means and having an output means on which appears a second output signal for the sequence control apparatus; and second logic select input means coupled to said second gating means for selecting a desired one of the output signals from said second state controller means to appear on the output means of the second gating means.

Claim 3

The sequence control apparatus of claim 1, also comprising: third gating means coupled to said second state controller means to receive a plurality of output signals from said second state controller means and having an output means on which appears a third output signal for the sequence control apparatus; and third logic select input means said third gating means for selecting a desired one of the output signals from the second state controller means to appear on the output of the third gating means.

Claim 4

The sequence control apparatus of claim 1, in which the devices of the state controller means and the second state controller means are flip flops.

Claim 5

The sequence control apparatus of claim 2, in which the devices of the state controller means and the second state controller means are flip flops.

Claim 6

Sequence control apparatus for providing a plurality of output signals selectively based upon either a rising edge of a clock signal or a falling edge of a clock signal, comprising: first, second, third and fourth bistable means, each having a reset input, a clock, input, a data input and a data output; means coupled the data output of the first bistable means to the data input of the third bistable means; means coupling the data output of the second bistable means to the data input of the fourth bistable means; clock input signal means coupled to the clock inputs of the first and third bistable means; clock inverter means having an input coupled to the clock input means and an output; means coupling the output of the clock inverter means to the clock inputs of the second and fourth bistable means; reset signal means coupled to the reset inputs of the first, second, third and fourth bistable means; start cycle input means coupled to the data inputs of the first and second bistable means; first, second, third and fourth gate means of a first type, said first gate means of the first type having one input coupled to an output of the first bistable means, said second gate means of the first type having one input coupled to an output of the second bistable means, said third gate means of the first type having one input coupled to an output of the third bistable means, and said fourth gate means of the first type having one input coupled to an output of the fourth bistable means; first logic second input means coupled to a second input of said first gate means of the first type of selecting the output of said first gate means of the first type; second logic select input means coupled to a second input of said second gate means of the first type for selecting the output of said second gate means of the first type; third logic select input means coupled to a second input of said third gate means of the first type for selecting the output of said third gate means of the first type; fourth logic select input means coupled to a second input of said fourth gate means of the first type for selecting the output of said fourth gate means of the first type; first gate means of a second type coupled to the outputs of said first and second gate means of the first type; second gate means of a second type coupled to the outputs of said third and fourth gate means of the first type; and first gate means of a third type coupled to the outputs of said first and second gate means of the second type and having output means on which appears an output signal for the sequence control apparatus.

Claim 7

Sequence control apparatus for providing a plurality of output signals selectively based upon either a rising edge of a clock signal or a falling edge of a clock signal, comprising: first, second, third and fourth bistable means, each having a reset input, a clock, input, a data input and a data output; means coupled the data output of the first bistable means to the data input of the third bistable means; means coupling the data output of the second bistable means to the data input of the fourth bistable means; clock input signal means coupled to the clock inputs of the first and third bistable means; clock inverter means having an input coupled to the clock input means and an output; means coupling the output of the clock inverter means to the clock inputs of the second and fourth bistable means; reset signal means coupled to the reset inputs of the first, second, third and fourth bistable means; start cycle input means coupled to the data inputs of the first and second bistable means; first, second, third and fourth gate means of a first type, said first gate means of the first type having one input coupled to an output of the first bistable means, said second gate means of the first type having one input coupled to an output of the second bistable means, said third gate means of the first type having one input coupled to an output of the third bistable means, and said fourth gate means of the first type having one input coupled to an output of the fourth bistable means; first logic second input means coupled to a second input of said first gate means of the first type of selecting the output of said first gate means of the first type; second logic select input means coupled to a second input of said second gate means of the first type for selecting the output of said second gate means of the first type; third logic select input means coupled to a second input of said third gate means of the first type for selecting the output of said third gate means of the first type; fourth logic select input means coupled to a second input of said fourth gate means of the first type for selecting the output of said fourth gate means of the first type; first gate means of a second type coupled to the outputs of said first and second gate means of the first type; second gate means of a second type coupled to the outputs of said third and fourth gate means of the first type; and first gate means of a third type coupled to the outputs of said first and second gate means of the second type and having output means on which appears an output signal for the sequence control apparatus.

Claim 8

The sequential control apparatus of claim 5, in which the bistable means are flip flops.

Claim 9

The sequential control apparatus of claim 5, in which the gate means of the first type are AND gates.

Claim 10

The sequential control apparatus of claim 5, in which the gate means of the second type are NOR gates.

Claim 11

The sequential control apparatus of claim 5, in which the gate means of the third type is a NAND gate.

Claim 12

The sequence control apparatus of claim 5, also comprising: fifth, sixth, seventh and eighth bistable means, each having a reset input, a clock input, a data input and a data output; means coupling the output of the first gate means of the third type to the data inputs of the fifth and sixth bistable means; means coupling the data output of the fifth bistable means to the data input of the seventh bistable means; means coupling the data output of the sixth bistable means to the data input of the eighth bistable means; means coupling the clock input signal means to the clock inputs of the fifth and seventh bistable means; means coupling the output of the clock inverter means to the clock inputs of the sixth and eighth bistable means; means coupling the reset signal means to the reset inputs of the fifth, sixth, seventh and eighth bistable means; fifth, sixth, seventh and eighth gate means the first type, said fifth gate means of the first type having an input coupled to an output of the fifth bistable means, said sixth gate means of the first type having an input coupled to an output of the sixth bistable means, said seventh gate means of the first type having an input coupled to an output of the seventh bistable means, and said eighth gate means of the first type having an input coupled to an output of the eighth bistable means; fifth logic select input means coupled to a second input of said fifth gate means of the first type; sixth logic select input means coupled to a second input of said sixth gate means of the first type; seventh logic select input means coupled to a second input of said seventh gate means of the first type; eighth logic select input means coupled to a second input of said eighth gate means of the first type; third gate means of the second type coupled to the outputs of said fifth and sixth gate means of the first type; fourth gate means of the second type coupled to the outputs of said seventh and eighth gate means of the first type; and second gate means of the third type coupled to the outputs of said third and fourth gate means of the second type and having output means on which appears an output signal for the sequence control apparatus.

Claim 13

The sequence control apparatus of claim 10, also comprising: ninth, tenth, eleventh and twelfth gate means of the first type, said ninth gate means of the first type having an input coupled to an output of the fifth bistable means, said tenth gate means of the first type having an input coupled to an output of the sixth bistable means, said eleventh gate means of the first type having an input coupled to an output of the seventh bistable means, and said twelfth gate means of the first type having an input coupled to an output of the eighth bistable means; ninth logic select input means coupled to a second input of said ninth gate means of the first type; tenth logic select input means coupled to a second input of said tenth gate means of the first type; eleventh logic select input means coupled to a second input of said eleventh gate means of the first type; twelfth logic select input means coupled to a second input of said twelfth gate means of the first type; fifth gate means of the second type coupled to the outputs of the ninth and tenth gate means of the first type; sixth gate means of the second type coupled to the outputs of the eleventh and twelfth gate means of the first type; and third gate means of the third type coupled to the outputs of said fifth and sixth gate means of the second type and having output means on which appears an output signal for the sequence control apparatus.

Claim 14

The sequential control apparatus of claim 10, in which the bistable means are flip flops.

Claim 15

The sequential control apparatus of claim 10, in which the gate means of the first type are AND gates.

Claim 16

The sequential control apparatus of claim 10, in which the gate means of the second type are NOR gates.

Claim 17

The sequential control apparatus of claim 10, in which the gate means of the third type are NAND gates.

Claim 18

The sequential control apparatus of claim 11, in which the bistable means are flip flops.

Claim 19

The sequential control apparatus of claim 11, in which the gate means of the first type are AND gates.

Claim 20

The sequential control apparatus of claim 11, in which the gate means of the second type are NOR gates.

Claim 21

The sequential control apparatus of claim 11, in which the gate means of the third type are NAND gates.

Claim 22

The sequential control apparatus of claim 11, in which the output of the first gate means of the third type is an activating signal for a memory row address strobe signal.

Claim 23

The sequential control apparatus of claim 11, in which the output of the second gate means of the third type is an activating signal for a multiplex address switch signal.

Claim 24

The sequential control apparatus of claim 11, in which the output of the third gate means of the third type is an activating signal for a memory column address strobe signal.

Claim 25

Sequence control apparatus for providing a plurality of output signals selectively based upon either a rising edge of a clock signal or a falling edge of a clock signal, comprising: first, second, third and fourth flip flop means each having a reset input, a clock input, a data input and a data output; means coupling the data output of the first flip flop means to the data input of the third flip flop means; means coupling the data output of the second flip flop means to the data input of the fourth flip flop means; clock input signal means coupled to the clock inputs of the first and third flip flop means; clock inverter means having an input coupled to the clock input means and an output; means coupling the output of the clock inverter means to the clock inputs of the second and fourth flip flop means; reset signal means coupled to the reset inputs of the first, second, third and fourth flip flop means; start cycle input means coupled to the data inputs of the first and second flip flop means; first, second, third and fourth AND gate means, said first AND gate means having one input coupled to an output of the first flip flop means, said second AND gate means having one input coupled to an output of the second flip flop means, said third AND gate means having one input coupled to an output of the third flip flop means, and said fourth AND gate means having one input coupled to an output of the fourth flip flop means; first logic select input means coupled to a second input of said first AND gate means for selecting the output of said first AND gate means; second logic select input means coupled to a second input of said second AND gate means for selecting the output of said second AND gate means; third logic select input means coupled to a second input of said third AND gate means for selecting the output of said third AND gate means; fourth logic select input means coupled to a second input of said fourth AND gate means for selecting the output of said fourth AND gate means; first NOR gate means coupled to the outputs of said first and second AND gate means; second NOR gate means coupled to the outputs of said third and fourth AND gate means; and NAND gate means coupled to the outputs of said first and second NOR gate means and having output means on which appears an output signal for the sequence control apparatus.

Claim 26

Sequence control apparatus for providing a plurality of output signals selectively based upon either a rising edge of a clock signal or a falling edge of a clock signal, comprising: first, second, third and fourth flip flop means each having a reset input, a clock input, a data input and a data output; means coupling the data output of the first flip flop means to the data input of the third flip flop means; means coupling the data output of the second flip flop means to the data input of the fourth flip flop means; clock input signal means coupled to the clock inputs of the first and third flip flop means; clock inverter means having an input coupled to the clock input means and an output; means coupling the output of the clock inverter means to the clock inputs of the second and fourth flip flop means; reset signal means coupled to the reset inputs of the first, second, third and fourth flip flop means; start cycle input means coupled to the data inputs of the first and second flip flop means; first, second, third and fourth AND gate means, said first AND gate means having one input coupled to an output of the first flip flop means, said second AND gate means having one input coupled to an output of the second flip flop means, said third AND gate means having one input coupled to an output of the third flip flop means, and said fourth AND gate means having one input coupled to an output of the fourth flip flop means; first logic select input means coupled to a second input of said first AND gate means for selecting the output of said first AND gate means; second logic select input means coupled to a second input of said second AND gate means for selecting the output of said second AND gate means; third logic select input means coupled to a second input of said third AND gate means for selecting the output of said third AND gate means; fourth logic select input means coupled to a second input of said fourth AND gate means for selecting the output of said fourth AND gate means; first NOR gate means coupled to the outputs of said first and second AND gate means; second NOR gate means coupled to the outputs of said third and fourth AND gate means; and NAND gate means coupled to the outputs of said first and second NOR gate means and having output means on which appears an output signal for the sequence control apparatus.