US5260892A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed electrical signal interconnect structure
Assignee: Sun Microsystems Inc
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Filing: 1991-11-21
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Granted: 1993-11-09
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Expires: 2011-11-21
Abstract
Abstract An improved high speed, high density Dynamic Random Access Memory (DRAM) electrical signal interconnect structure which has particular application to computer systems which employ Single In-line Memory Modules (SIMMs). The structure contains an on-board buffer for driving time critical signals from a single source and further includes innovative signal trace routing having approximately equivalent minimum distance signal line lengths and vias to memory modules on the front and back surfaces of the circuit board resulting in a high speed, high density SIMM with clean rising/falling signal edges.
Inventors
- 👤 James Testa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:30
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/40; H10D86/441; G; G11; G11C; G11C7/00; G11C7/10; G11C5/00; G11C5/06; G11C5/063; G11C7/22; H05; H05K; H05K1/00; H05K1/18; H05K2201/00; H05K2201/10; H05K2201/10007; H05K2201/10159; H05K2201/10431; H05K2201/10507; H05K2201/10545; H05K2201/10613; H05K2201/10621; H05K2201/10689
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
211 words
A computer memory module having at least one control signal, said at least one control signal synchronized by a clock pulse, said clock pulse having a rise time period wherein said clock pulse changes from a first voltage level to a second voltage level, said memory module comprising: a circuit board; a driving integrated circuit (IC) mounted to said circuit board, said driving IC for amplifying said at least one control signal; a plurality of random access memory (RAM) integrated circuits (ICs) for storing data, each said RAM IC mounted to said circuit board; and first coupling means for electrically coupling said driving IC to each said RAM IC, said first coupling means thereby providing said at least one control signal to each said RAM IC, said driving IC and said plurality of RAM ICs mounted on said circuit board in a pattern such that the distance from said driving IC to each said RAM IC is sufficiently short such that when said at least one control signal, driven by said driving IC, reflects back from each said RAM IC, said reflected at least one control signal combines with said at least one control signal within said rise time period thereby eliminating false triggers of said at least one control signal.
Claim 2
Dependent Claim
211 words
A computer memory module having at least one control signal, said at least one control signal synchronized by a clock pulse, said clock pulse having a rise time period wherein said clock pulse changes from a first voltage level to a second voltage level, said memory module comprising: a circuit board; a driving integrated circuit (IC) mounted to said circuit board, said driving IC for amplifying said at least one control signal; a plurality of random access memory (RAM) integrated circuits (ICs) for storing data, each said RAM IC mounted to said circuit board; and first coupling means for electrically coupling said driving IC to each said RAM IC, said first coupling means thereby providing said at least one control signal to each said RAM IC, said driving IC and said plurality of RAM ICs mounted on said circuit board in a pattern such that the distance from said driving IC to each said RAM IC is sufficiently short such that when said at least one control signal, driven by said driving IC, reflects back from each said RAM IC, said reflected at least one control signal combines with said at least one control signal within said rise time period thereby eliminating false triggers of said at least one control signal.
Claim 3
Dependent Claim
23 words
The memory module as set forth in claim 1 wherein said at least one control signal comprises a row address strobe (RAS) signal.
Claim 4
Dependent Claim
23 words
The memory module as set forth in claim 1 wherein said at least one control signal comprises a column address strobe (CAS) signal.
Claim 5
Dependent Claim
22 words
The memory module as set forth in claim 1 wherein said at least one control signal comprises a write enable (WE) signal.
Claim 6
Dependent Claim
162 words
The memory module as set forth in claim 1 wherein said circuit board has a first and second surface, and wherein said driving IC and said plurality of RAM ICs are mounted on said first surface, said circuit board further comprising: RAM means for storing data, said RAM means being mounted to said second surface; second coupling means for electrically coupling said first coupling means to said RAM means, said first and second coupling means together thereby providing said at least one control signal to said RAM means, said RAM means mounted on said circuit board such that the distance from said driving IC to said RAM means is sufficiently short such that when said at least one control signal, driven by said driving IC, reflects back from said RAM means, said reflected at least one control signal combines with said at least one control signal within said rise time period thereby eliminating false triggers of said at least one control signal.
Claim 7
Dependent Claim
53 words
The memory module as set forth in claim 5 wherein said RAM means comprises a plurality of second-side RAM ICs mounted on said second surface equal in number to the number of said RAM ICs mounted on said first surface, such that each of said second-side RAM IC has a corresponding RAM IC.
Claim 8
Dependent Claim
24 words
The memory module as set forth in claim 6 wherein each said second-side RAM IC is a mirror of its said corresponding RAM IC.
Claim 9
Dependent Claim
317 words
A computer memory module having at least one control signal, said at least one control signal synchronized by a clock pulse, said clock pulse having a rise time period wherein said clock pulse changes from a first voltage level to a second voltage level, said memory module comprising: a circuit board, said circuit board having a first and second surface; a driving integrated circuit (IC) mounted to said first surface, said driving IC for amplifying said at least one control signal; a plurality of random access memory (RAM) integrated circuits (ICs) for storing data, each said RAM IC mounted to said first surface; first coupling means for electrically coupling said driving IC to each said RAM IC, said first coupling means thereby providing said at least one control signal to each said RAM IC, said driving IC and said plurality of RAM ICs mounted on said circuit board in a pattern such that the distance from said driving IC to each said RAM IC is sufficiently short such that when said at least one control signal, driven by said driving IC, reflects back from each said RAM IC, said reflected at least one control signal combines with said at least one control signal within said rise time period; RAM means for storing data, said RAM means mounted to said second surface; second coupling means for electrically coupling said first coupling means to said RAM means, said first and second coupling means together thereby providing said at least one control signal to said RAM means, said RAM means mounted on said circuit board such that the distance from said driving IC to said RAM means is sufficiently short such that when said at least one control signal, driven by said driving IC, reflects back from said RAM means, said reflected at least one control signal combines with said at least one control signal within said rise time period.
Claim 10
Dependent Claim
317 words
A computer memory module having at least one control signal, said at least one control signal synchronized by a clock pulse, said clock pulse having a rise time period wherein said clock pulse changes from a first voltage level to a second voltage level, said memory module comprising: a circuit board, said circuit board having a first and second surface; a driving integrated circuit (IC) mounted to said first surface, said driving IC for amplifying said at least one control signal; a plurality of random access memory (RAM) integrated circuits (ICs) for storing data, each said RAM IC mounted to said first surface; first coupling means for electrically coupling said driving IC to each said RAM IC, said first coupling means thereby providing said at least one control signal to each said RAM IC, said driving IC and said plurality of RAM ICs mounted on said circuit board in a pattern such that the distance from said driving IC to each said RAM IC is sufficiently short such that when said at least one control signal, driven by said driving IC, reflects back from each said RAM IC, said reflected at least one control signal combines with said at least one control signal within said rise time period; RAM means for storing data, said RAM means mounted to said second surface; second coupling means for electrically coupling said first coupling means to said RAM means, said first and second coupling means together thereby providing said at least one control signal to said RAM means, said RAM means mounted on said circuit board such that the distance from said driving IC to said RAM means is sufficiently short such that when said at least one control signal, driven by said driving IC, reflects back from said RAM means, said reflected at least one control signal combines with said at least one control signal within said rise time period.
Claim 11
Dependent Claim
23 words
The memory module as set forth in claim 8 wherein said at least one control signal comprises a row address strobe (RAS) signal.
Claim 12
Dependent Claim
23 words
The memory module as set forth in claim 8 wherein said at least one control signal comprises a column address strobe (CAS) signal.
Claim 13
Dependent Claim
22 words
The memory module as set forth in claim 8 wherein said at least one control signal comprises a write enable (WE) signal.
Claim 14
Dependent Claim
53 words
The memory module as set forth in claim 8 wherein said RAM mans comprises a plurality of second-side RAM ICs mounted on said second surface equal in number to the number of said RAM ICs mounted on said first surface, such that each of said second-side RAM IC has a corresponding RAM IC.
Claim 15
Dependent Claim
24 words
The memory module as set forth in claim 12 wherein each said second-side RAM IC is a mirror of its said corresponding RAM IC.
Claim 16
Dependent Claim
201 words
In a computer memory module having at least one control signal, said at least one control signal synchronized by a clock pulse, said clock pulse having a rise time period wherein said clock pulse changes from a first voltage level to a second voltage level, a method of eliminating false triggers of at least one control signal, said method comprising the steps of: providing a circuit board; mounting to said circuit board a driving integrated circuit (IC) for amplifying said at least one control signal; mounting to said circuit board a plurality of random access memory (RAM) integrated circuits (ICs) for storing data; and coupling said driving IC to each said RAM IC thereby providing said at least one control signal to each said RAM IC, said driving IC and said plurality of RAM ICs being mounted on said circuit board in a pattern such that the distance from said driving IC to each said RAM IC is sufficiently short such that when said at least one control signal, driven by said driving IC, reflects back from each said RAM IC, said reflected at least one control signal combines with said at least one control signal within said rise time period.
Claim 17
Dependent Claim
201 words
In a computer memory module having at least one control signal, said at least one control signal synchronized by a clock pulse, said clock pulse having a rise time period wherein said clock pulse changes from a first voltage level to a second voltage level, a method of eliminating false triggers of at least one control signal, said method comprising the steps of: providing a circuit board; mounting to said circuit board a driving integrated circuit (IC) for amplifying said at least one control signal; mounting to said circuit board a plurality of random access memory (RAM) integrated circuits (ICs) for storing data; and coupling said driving IC to each said RAM IC thereby providing said at least one control signal to each said RAM IC, said driving IC and said plurality of RAM ICs being mounted on said circuit board in a pattern such that the distance from said driving IC to each said RAM IC is sufficiently short such that when said at least one control signal, driven by said driving IC, reflects back from each said RAM IC, said reflected at least one control signal combines with said at least one control signal within said rise time period.
Claim 18
Dependent Claim
22 words
The method as set forth in claim 14 wherein said at least one control signal comprises a row address strobe (RAS) signal.
Claim 19
Dependent Claim
22 words
The method as set forth in claim 14 wherein said at least one control signal comprises a column address strobe (CAS) signal.
Claim 20
Dependent Claim
21 words
The method as set forth in claim 14 wherein said at least one control signal comprises a write enable (WE) signal.
Claim 21
Dependent Claim
134 words
The method as set forth in claim 14 wherein said circuit board has a first and second surface, and wherein said driving IC and said plurality of RAM ICs are mounted on said first surface, said method further comprising the steps of: mounting RAM means on said second surface, said RAM means for storing data; coupling said driving IC to said RAM means thereby providing said at least one control signal to said RAM means, said RAM means mounted such that the distance from said driving IC to said RAM means is sufficiently short such that when said at least one control signal, driven by said driving IC, reflects back from said RAM means, said reflected at least one control signal combines with said at least one control signal within said rise time period.
Claim 22
Dependent Claim
51 words
The method as set forth in claim 18 wherein said RAM means comprises a plurality of second-side RAM ICs mounted on said second surface, equal in number to the number of said RAM ICs mounted on said first surface, such that each said second-side RAM IC has a corresponding RAM IC.
Claim 23
Dependent Claim
23 words
The method as set forth in claim 19 wherein each said second-side RAM IC is a mirror of its said corresponding RAM IC.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-08 | 1997-05-10 | 1997-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-08 | 2001-05-10 | 2001-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-08 | 2005-05-10 | 2005-11-09 | $7700.00 | Window Closed / Lapsed |