US4879631A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Short-resistant decoupling capacitor system for semiconductor circuits
Assignee: Micron Technology Inc
•
Filing: 1989-01-18
•
Granted: 1989-11-07
•
Expires: 2009-01-18
Abstract
Abstract A decoupling capacitor system for improving the reliability of digital logic circuit boards such as single inline memory modules which use surface-mount decoupling capacitors. The system comprises one or more units of two or more series-connected capacitors connected between the chip supply voltage (Vcc) input and the chip ground (Vss) connection. Given no change in the reliability of the individual capacitors, the reliability of a circuit board can typically be improved by several order of magnitude.
Inventors
- 👤 Gary M. Johnson
- 👤 Leland R. Nevill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:32
CPC Classifications
G; G11; G11C; G11C5/00; H; H05; H05K; H05K1/00; H05K1/02; H05K1/0213; H05K1/0216; H05K1/023; H05K1/0231; H05K1/14; H05K1/141; H05K2201/00; H05K2201/10; H05K2201/10431; H05K2201/10507; H05K2201/10515; H05K2201/10613; H05K2201/10621; H05K2201/10689
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
57 words
In combination with a digital memory expansion board having an array of row-and-column-addressable memory cells, which is designed to be directly connected in parallel with the data, address, Vcc and Vss buses of a computer, a decoupling capacitor system on said board connected between the Vcc bus and the Vss bus comprising two or more series-connected capacitors.
Claim 2
Dependent Claim
57 words
In combination with a digital memory expansion board having an array of row-and-column-addressable memory cells, which is designed to be directly connected in parallel with the data, address, Vcc and Vss buses of a computer, a decoupling capacitor system on said board connected between the Vcc bus and the Vss bus comprising two or more series-connected capacitors.
Claim 3
Dependent Claim
32 words
The decoupling capacitor system of claim 1 which further comprises multiple units of two or more series-connected capacitors, said units being connected in parallel between the Vcc bus and the Vss bus.
Claim 4
Dependent Claim
33 words
The decoupling capacitor system of claim 1, wherein said array is a multiple-byte configuration comprised of essentially identical memory chips, with each memory chip contributing one bit to each addressable byte of information.
Claim 5
Dependent Claim
17 words
The decoupling capacitor system of claim 3, wherein said array is a single inline memory module (SIMM).
Claim 6
Dependent Claim
16 words
The decoupling capacitor system of claim 3, wherein said array is a single inline package (SIP).
Claim 7
Dependent Claim
19 words
The decoupling capacitor system of claim 1, wherein said memory expansion module is a single inline memory module (SIMM).
Claim 8
Dependent Claim
18 words
The decoupling capacitor system of claim 1, wherein said memory expansion module is a single inline package (SIP).
Claim 9
Dependent Claim
25 words
The decoupling capacitor system of claim 1, wherein information is stored into the array and retrieved from the array with high and low-state voltage signals.
Claim 10
Dependent Claim
29 words
In combination with a circuit-board-mounted array of row-and-column-addressable digital logic components, a decoupling capacitor system between a Vcc bus and a Vss bus comprising two or more series-connected capacitors.
Claim 11
Dependent Claim
29 words
In combination with a circuit-board-mounted array of row-and-column-addressable digital logic components, a decoupling capacitor system between a Vcc bus and a Vss bus comprising two or more series-connected capacitors.
Claim 12
Dependent Claim
32 words
The decoupling capacitor system of claim 9 Which further comprises multiple units of two or more series-connected capacitors, said units being connected in parallel between the Vcc bus and the Vss bus.
Claim 13
Dependent Claim
16 words
The decoupling capacitor system of claim 9, wherein said array is comprised of gate array chips.
Claim 14
Dependent Claim
57 words
In combination with a digital memory expansion board having a series of essentially identical memory chips, each of which provides one bit of information for each byte or word of information stored on said board, a decoupling capacitor system on said board connected between a Vcc bus and a Vss bus comprising two or more series-connected capacitors.
Claim 15
Dependent Claim
57 words
In combination with a digital memory expansion board having a series of essentially identical memory chips, each of which provides one bit of information for each byte or word of information stored on said board, a decoupling capacitor system on said board connected between a Vcc bus and a Vss bus comprising two or more series-connected capacitors.
Claim 16
Dependent Claim
32 words
The decoupling capacitor system of claim 12 which further comprises multiple units of two or more series-connected capacitors, said units being connected in parallel between the Vcc bus and the Vss bus.
Claim 17
Dependent Claim
18 words
The decoupling capacitor system of claim 13 wherein each of said series-connected capacitors is of the surface-mount type.
Claim 18
Dependent Claim
19 words
The decoupling capacitor system of claim 14, wherein each of said series-connected capacitors is mounted beneath said memory chips.
References Cited (Backward Citations)
US3402372A
Cited
US3859592A
Cited
US3909638A
Cited
US4386327A
Cited
US4577215A
Cited
GB2152753A
Cited
US4744008A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-06 | 1993-05-08 | 1993-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-06 | 1997-05-08 | 1997-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-06 | 2001-05-08 | 2001-11-07 | $7700.00 | Window Closed / Lapsed |