Logic circuit for controlling a supply on drive pulses to regulate an output level

Claim 2

A logic circuit comprising an emitter-follower circuit, an active pull-down circuit which pulls down the potential of the output of said emitter-follower circuit in response to the change in the input level of said emitter-follower circuit, an output level detection circuit which detects a change in the potential of the output end of said emitter-follower circuit from a high level to a low level, control means for controlling an energization of said active pull-down circuit in response to the detected result of said output level detection circuit, said output detection circuit including first switching means provided between an output of said output level detection circuit and a first power supply, and means for generating a detection signal in response to the output of said first switching means, the energization of said first switching means being controlled in response to a potential level at an output end of said emitter-follower circuit, said control means being provided between the input end of said active pull-down circuit and a second power supply and including second switching means, the energization of said second switching means being controlled in response to said detection signal.

Claim 3

A logic circuit as claimed in claim 1, wherein said active pull-down circuit includes third switching means provided between the output end of said emitter-follower circuit and said second power supply, and the switching of said third switching means being controlled in response to the change in the input level of said emitter-follower circuit and further to an output of said third switching means.

Claim 4

A logic circuit as claimed in claim 1, wherein said second switching means is a bipolar transistor.

Claim 5

A logic circuit as claimed in claim 1, wherein said second switching means is an MOS transistor.

Claim 6

A logic circuit comprising an output stage transistor having a collector connected to a first power supply, said output stage transistor having an emitter connected to an output terminal, and said output stage transistor having a base connected to an input terminal, an active transistor connected between said output terminal and a second power supply, the energization of said active transistor being controlled in response to a control signal, and control means for detecting a potential change at said output terminal and generating said control signal in response to the detected result, said control means including first switching means provided between the output of said control means and said first power supply, and second switching means provided between said output terminal and said second power supply, the energization of said first switching means being controlled in response to the potential of said output terminal, and the switching of said second switching means being controlled in response to the output of said first switching means.

Claim 7

A logic circuit comprising an output stage transistor having a collector connected to a first power supply, said output stage transistor having an emitter connected to an output terminal, and said output stage transistor having a base connected to an input terminal, an active transistor connected between said output terminal and a second power supply, the energization of said active transistor being controlled in response to a control signal, and control means for detecting a potential change at said output terminal and generating said control signal in response to the detected result, said control means including first switching means provided between the output of said control means and said first power supply, and second switching means provided between said output terminal and said second power supply, the energization of said first switching means being controlled in response to the potential of said output terminal, and the switching of said second switching means being controlled in response to the output of said first switching means.

Claim 8

A logic circuit comprising a first transistor having a control electrode and being connected between a first power terminal and an output terminal, a second transistor having a control electrode and being connected between said output terminal and a second power terminal, a drive circuit coupled to the control electrodes of said first and second transistors, said drive circuit being responsive to an input signal for supplying a first drive signal to the control electrode of said first transistor to cause said first transistor to charge said output terminal when said input signal takes a first logic level and for supplying a second drive signal to the control electrode of said second transistor to cause said second transistor to discharge said output terminal when said input signal takes a second logic level, a third transistor having a control electrode and being connected between the control electrode of said second transistor and said second power terminal, and an output level detection circuit coupled to said output terminal and the control electrode of said third transistor and operating responsive to detected levels for discharging said second transistor for driving said third transistor so that said third transistor suppresses the supply of said second drive signal from said drive circuit to the control electrode of said second transistor in order to lower the energization of said second transistor.

Claim 9

A logic circuit comprising a first transistor having a control electrode and being connected between a first power terminal and an output terminal, a second transistor having a control electrode and being connected between said output terminal and a second power terminal, a drive circuit coupled to the control electrodes of said first and second transistors, said drive circuit being responsive to an input signal for supplying a first drive signal to the control electrode of said first transistor to cause said first transistor to charge said output terminal when said input signal takes a first logic level and for supplying a second drive signal to the control electrode of said second transistor to cause said second transistor to discharge said output terminal when said input signal takes a second logic level, a third transistor having a control electrode and being connected between the control electrode of said second transistor and said second power terminal, and an output level detection circuit coupled to said output terminal and the control electrode of said third transistor and operating responsive to detected levels for discharging said second transistor for driving said third transistor so that said third transistor suppresses the supply of said second drive signal from said drive circuit to the control electrode of said second transistor in order to lower the energization of said second transistor.

Claim 10

The logic circuit as claimed in claim 6, wherein said output level detection circuit includes a bias resistor connected between the control electrode of said third transistor and said second power terminal and a fourth transistor connected between the control electrode of said third transistor and said first power terminal and having a control electrode coupled to said output terminal.

Claim 11

The logic circuit as claimed in claim 7, wherein each of said first, second and third transistors has a first conductivity type and said fourth transistor has a second conductivity type which is opposite to said first conductivity type.