ECL to TTL translator circuit with improved slew rate

Claim 2

An ECL to TTL translator circuit comprising: an ECL gate having differential ECL inputs for receiving ECL input signals of high and low potential levels at least at one of the ECL inputs (V IN ), and differential first and second ECL output nodes (A,B); first and second emitter follower output circuits coupled to the respective first and second ECL output nodes; a TTL gate (12) having a TTL output (V OUT ) for delivering TTL output signals corresponding to ECL input signals received at least at one of the ECL inputs; said TTL gate having a phase splitter transistor element (Q9) coupled in the TTL gate (12) to control the TTL output (V OUT ) according to the conducting state of the phase splitter transistor element; and a voltage amplifier transistor element (Q6) having a collector node coupled to a base node of the phase splitter transistor element (Q9) for controlling the conducting state of the phase splitter transistor element out of phase with the voltage amplifier transistor element; said first emitter follower output circuit being coupled to a base node of the voltage amplifier transistor element (Q6) and said second emitter follower output circuit being coupled to the collector node of the voltage amplifier transistor element (Q6) for switching on and off the voltage amplifier transistor element in accordance with ECL input signals; the base node of the voltage amplifier transistor element (Q6) being coupled to a low potential power rail (GND) through voltage drop component means including a resistor (R8,R11) for variable control of the voltage level at said base node.

Claim 3

The ECL to TTL translator circuit of claim 1 wherein the first emitter follower output circuit comprises a first stack of voltage drop component elements (Q7,Q8,R4,D4,R8) defining a first switching control node (C) coupled to the base node of the voltage amplifier transistor element (Q6), said first switching control node (C) being coupled to the low potential power rail (GND) through said resistor (R8,R11) for variable control of the voltage level at said first switching control node (C).

Claim 4

The ECL to TTL translator of claim 2 wherein the second emitter follower output circuit comprises a second stack of voltage drop component elements (Q3,Q4,R3,Q6,D6), said voltage amplifier transistor element (Q6) having collector and emitter nodes coupled in the second stack, said second stack of voltage drop component elements defining at the collector node of the voltage amplifier transistor element (Q6) a second switching control node (D) coupled to the base node of the phase splitter transistor element (Q9).

Claim 5

The TTL to ECL translator circuit of claim 3 wherein the translator circuit is coupled between high and low potential power rails, wherein the TTL gate (12) comprises a lower output pulldown transistor element (QLOP) having base and emitter nodes coupled between an emitter node of the phase splitter transistor element (Q9) and the low potential power rail, and wherein the first and second stacks of the first and second emitter follower output circuits comprise voltage drop component elements selected to establish at the second switching control node (D) a high potential level signal >2V be above the low potential power rail (GND), and a low potential level signal <2V be above the low potential power rail (GND) according to the ECL input signals at least at one of the differential ECL inputs for switching the phase splitter transistor element on and off.

Claim 6

The ECL to TTL translator circuit of claim 4 wherein the voltage drop component elements of the second stack comprise a Schottky diode (D6) coupled between the emitter node of the voltage amplifier transistor element (Q6) and the low potential power rail and wherein the voltage drop component elements of the first voltage stack are selected to establish at the first switching control node (C) a high potential level signal >1V BE +1V SD above the low potential power rail and a low potential level signal <1V BE +1V SD above the low potential power rail in response to the ECL input signals at least at one of the differential ECL inputs for switching the voltage amplifier transistor element (Q6) on and off.

Claim 7

The ECL to TTL translator circuit of claim 4 further comprising a Miller killer transistor element (Q10) having collector and emitter nodes coupled between the base node of the lower output pulldown transistor element (QLOP) and the low potential power rail, said first stack of voltage drop components of the first emitter follower output circuit defining a third switching control node (E) at lower potential than the first switching control node (C) and separated from the first switching control node (C) by a voltage drop component (D4), said third switching control node (E) being coupled to the base node of the Miller killer transistor element (Q10) for switching the Miller killer translator element on and off in phase with the voltage amplifier transistor element (Q6).

Claim 8

The ECL to TTL translator circuit of claim 6 wherein the first (C) and third (E) switching control nodes are separated in the first stack by a diode element (D4) and wherein the third switching control node (E) is coupled to the low potential power rail (GND) through said resistor (R8).

Claim 9

The ECL to TTL translator circuit of claim 6 wherein the voltage drop component elements of the first stack are selected to establish at the third switching control node (E) a high potential level signal >1V be above the low potential power rail and a low potential level <1V be above the low potential power rail in response to ECL input signals at least at one of the differential ECL inputs for switching on and off the Miller killer transistor element (Q10) in phase with the voltage amplifier transistor element (Q6).

Claim 10

The ECL to TTL translator circuit of claim 3 wherein the TTL gate (12) comprises a lower output pulldown transistor element (QLOP) having base and emitter nodes coupled between an emitter node of the phase splitter transistor element (Q9) and a low potential power rail, and further comprising a Miller killer transistor element (Q10) having collector and emitter nodes coupled between the base node of the lower output pulldown transistor element (QLOP) and the low potential power rail, said first emitter follower output circuit first stack of voltage drop component elements defining a third switching control node (E) at lower potential than the first switching control node (C) and separated from the first switching control node (C) by a voltage drop component (D4), said third switching control node (E) being coupled to a base node of the Miller killer transistor element (Q10).

Claim 11

The ECL to TTL translator circuit of claim 9 wherein the first (C) and third (E) switching control nodes are separated by a Schottky diode voltage drop component element (D4) and wherein the third switching control node (E) is coupled to a low potential power rail (GND) through said resistor (R8).

Claim 12

The TTL to ECL translator circuit of claim 9 wherein the voltage drop component elements of the first and second stacks are selected to establish at the third control node (E) a high potential level signal >1V be above the low potential power rail and a low potential level <1V be above the low potential power rail in response to ECL input signals at least at one of the ECL inputs for switching on and off the Miller killer transistor element (Q10).

Claim 13

An ECL to TTL translator circuit having an ECL input gate (Q1,Q2) with differential ECL inputs (V in , V in ) for receiving ECL input signals, and differential first and second ECL output nodes (A,B), first and second emitter follower output circuits (Q3, Q7) respectively coupled to the first and second ECL output nodes (A,B), a TTL gate (12) having a TTL output (V out ) for delivering TTL output signals corresponding to ECL input signals at least at one of the ECL inputs (V in , V in ), said TTL gate (12) having a phase splitter transistor element (Q9) coupled to control the TTL output according to the conducting state of the phase splitter transistor element the improvement comprising: said second emitter follower output circuit (Q3) comprising a second stack of voltage drop component elements (Q4,R3,Q6,D3), including a voltage amplifier transistor element (Q6) having collector and emitter nodes coupled in the second stack; said first emitter follower output circuit (Q7) comprising a first stack of voltage drop component elements (Q8,R4,D4,R8), (Q8, R4, R11, Q11) defining a first switching control node (C), said first switching control node (C) being coupled to a base node of the voltage amplifier transistor element (Q6) in the second emitter follower output circuit for switching on and off the voltage amplifier transistor element (Q6), said first switching control node (C) being coupled to a low potential power rail (GND) by voltage drop components of the first stack including a resistor (R8,R11) for variable control of the voltage level at said first switching control node (C); the collector node of the voltage amplifier transistor element (Q6) forming a second control node (D) in the second emitter follower output circuit coupled to the base node of the phase splitter transistor element (Q9) for switching on and off the phase splitter transistor element (Q9) out of phase with the voltage amplifier transistor element (Q6).

Claim 14

An ECL to TTL translator circuit having an ECL input gate (Q1,Q2) with differential ECL inputs (V in , V in ) for receiving ECL input signals, and differential first and second ECL output nodes (A,B), first and second emitter follower output circuits (Q3, Q7) respectively coupled to the first and second ECL output nodes (A,B), a TTL gate (12) having a TTL output (V out ) for delivering TTL output signals corresponding to ECL input signals at least at one of the ECL inputs (V in , V in ), said TTL gate (12) having a phase splitter transistor element (Q9) coupled to control the TTL output according to the conducting state of the phase splitter transistor element the improvement comprising: said second emitter follower output circuit (Q3) comprising a second stack of voltage drop component elements (Q4,R3,Q6,D3), including a voltage amplifier transistor element (Q6) having collector and emitter nodes coupled in the second stack; said first emitter follower output circuit (Q7) comprising a first stack of voltage drop component elements (Q8,R4,D4,R8), (Q8, R4, R11, Q11) defining a first switching control node (C), said first switching control node (C) being coupled to a base node of the voltage amplifier transistor element (Q6) in the second emitter follower output circuit for switching on and off the voltage amplifier transistor element (Q6), said first switching control node (C) being coupled to a low potential power rail (GND) by voltage drop components of the first stack including a resistor (R8,R11) for variable control of the voltage level at said first switching control node (C); the collector node of the voltage amplifier transistor element (Q6) forming a second control node (D) in the second emitter follower output circuit coupled to the base node of the phase splitter transistor element (Q9) for switching on and off the phase splitter transistor element (Q9) out of phase with the voltage amplifier transistor element (Q6).

Claim 15

The TTL to ECL translator circuit of claim 12 wherein the translator circuit is coupled between high and low potential power rails, wherein the TTL gate (12) comprises a lower output pulldown transistor element (QLOP) having base and emitter nodes coupled between an emitter node of the phase splitter transistor element (Q9) and the low potential power rail, and wherein the first and second stacks of the first and second emitter follower output circuits comprise voltage drop component elements selected to establish at the second control node (D) a high potential level signal >2V be above the low potential power rail, and a low potential level signal <2V be above the low potential power rail according to the ECL input signals at the differential ECL inputs for switching the phase splitter transistor element on and off.

Claim 16

The ECL to TTL translator circuit of claim 13 wherein the voltage drop component elements of the second voltage drop stack comprise a Schottky diode (D6) couple between the emitter node of the voltage amplifier transistor element (Q6) and the low potential power rail and wherein the voltage drop component elements of the first voltage stack are selected to establish at the first switching control node (C) a high potential level signal >1V BE +1V SD above the low potential power rail and a low potential level signal <1V BE +1V SD above the low potential power rail in response to the ECL input signals at least at one of the differential ECL inputs for switching the voltage amplifier transistor element on and off.

Claim 17

The ECL to TTL translator circuit of claim 13 further comprising a Miller killer transistor element (Q10) having collector and emitter nodes coupled between the base node of the lower output pulldown transistor element (QLOP) and the low potential power rail, said first emitter follower output circuit defining a third switching control node (E) at lower potential then the first switching control node (C) and separated from the first switching control node (C) by a voltage drop component (D4), said third switching control node (E) being coupled to the base node of the Miller killer transistor element for switching the Miller killer transistor element (Q10) on and off in phase with the voltage amplifier transistor element (Q6), said third switching control node (E) being coupled to the low potential power rail (GND) through said resistor (R8,R11).

Claim 18

The ECL to TTL translator circuit of claim 15 wherein the voltage drop component elements of the first stack are selected to establish at the third switching control node (E) a high potential level signal >1V be above the low potential power rail and a low potential level <1V be above the low potential power rail in response to ECL input signals at least at one of the differential ECL inputs for switching on and off the Miller killer transistor element (Q10) in phase with the voltage amplifier transistor element (Q6).