US4644194A
Expired / Lapsed
US
⏱️ 0.0 years remaining
ECL to TTL voltage level translator
Assignee: Semiconductor Components Industries LLC
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Filing: 1985-06-24
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Granted: 1987-02-17
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Expires: 2005-06-24
Abstract
Abstract A voltage level translator circuit is provided that translates an input voltage referenced to an ECL supply voltage V CC to a voltage referenced to a TTL supply voltage V EE independent of power supply voltage variations. A first and a second embodiment have reference circuits coupled to receive a data input signal for providing a single signal referenced to a first supply voltage terminal to a current mirror. An output circuit is coupled to the current mirror for providing an output signal referenced to the second supply voltage terminal. A third embodiment has a reference circuit coupled to receive a data input signal for referencing a voltage on a first supply voltage terminal to a voltage on a second supply voltage terminal. A voltage setting circuit is coupled to the reference circuit for setting a voltage within the reference circuit. An output circuit is coupled to the voltage setting circuit for providing an output voltage referenced to a voltage on the second voltage terminal and independent of variations in supply voltages.
Inventors
- 👤 Mark S. Birrittella
- 👤 Robert R. Marley
- 👤 Walter C. Seelbach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:27
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00369; H03K19/00376; H03K19/0175; H03K19/018; H03K19/01806; H03K19/01812
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
232 words
A voltage level translator circuit having a first supply voltage terminal and a second supply voltage terminal, comprising: first means coupled between said first and second supply voltage terminals and coupled to receive a data input signal, for providing a signal referenced to said first supply voltage terminal; second means coupled between said first and second supply voltage terminals for providing an output signal referenced to said second supply voltage terminal; a first resistor; a second resistor; a third resistor; a fourth resistor; a diode; a first transistor having a base coupled to said first supply voltage terminal by said first resistor, a collector coupled to said first supply voltage terminal, and an emitter coupled to said second means by said second resistor; a second transistor having a collector coupled to said second means, an emitter coupled to said second supply voltage terminal, and a base coupled to said second supply voltage terminal by said diode; a third transistor having a base coupled to said first means for receiving said signal, a collector coupled to aid first supply voltage terminal, and an emitter coupled to said base of said second transistor by said third resistor; and a fourth transistor having a base coupled for receiving a reference voltage, a collector coupled to said base of said first transistor, and an emitter coupled to said second supply voltage terminal by said fourth resistor.
Claim 2
Dependent Claim
232 words
A voltage level translator circuit having a first supply voltage terminal and a second supply voltage terminal, comprising: first means coupled between said first and second supply voltage terminals and coupled to receive a data input signal, for providing a signal referenced to said first supply voltage terminal; second means coupled between said first and second supply voltage terminals for providing an output signal referenced to said second supply voltage terminal; a first resistor; a second resistor; a third resistor; a fourth resistor; a diode; a first transistor having a base coupled to said first supply voltage terminal by said first resistor, a collector coupled to said first supply voltage terminal, and an emitter coupled to said second means by said second resistor; a second transistor having a collector coupled to said second means, an emitter coupled to said second supply voltage terminal, and a base coupled to said second supply voltage terminal by said diode; a third transistor having a base coupled to said first means for receiving said signal, a collector coupled to aid first supply voltage terminal, and an emitter coupled to said base of said second transistor by said third resistor; and a fourth transistor having a base coupled for receiving a reference voltage, a collector coupled to said base of said first transistor, and an emitter coupled to said second supply voltage terminal by said fourth resistor.
Claim 3
Dependent Claim
232 words
A voltage level translator circuit having a first supply voltage terminal and a second supply voltage terminal, comprising: first means coupled between said first and second supply voltage terminals and coupled to receive a data input signal, for providing a signal referenced to said first supply voltage terminal; second means coupled between said first and second supply voltage terminals for providing an output signal referenced to said second supply voltage terminal; a first resistor; a second resistor; a third resistor; a fourth resistor; a diode; a first transistor having a base coupled to said first means for receiving said signal, a collector coupled to said first supply voltage terminal, and an emitter coupled to said second means by said first resistor; a second transistor having a collector coupled to said second means, an emitter coupled to said second supply voltage terminal, and a base coupled to said second supply voltage terminal by said diode; a third transistor having a base coupled to receive a reference voltage, a collector coupled to said first supply voltage terminal by said second resistor, and an emitter coupled to said second supply voltage terminal by said third resistor; and a fourth transistor having a base coupled to said collector of said third transistor, a collector coupled to said first supply voltage terminal, and an emitter coupled to said base of said second transistor by said fourth resistor.
Claim 4
Dependent Claim
232 words
A voltage level translator circuit having a first supply voltage terminal and a second supply voltage terminal, comprising: first means coupled between said first and second supply voltage terminals and coupled to receive a data input signal, for providing a signal referenced to said first supply voltage terminal; second means coupled between said first and second supply voltage terminals for providing an output signal referenced to said second supply voltage terminal; a first resistor; a second resistor; a third resistor; a fourth resistor; a diode; a first transistor having a base coupled to said first means for receiving said signal, a collector coupled to said first supply voltage terminal, and an emitter coupled to said second means by said first resistor; a second transistor having a collector coupled to said second means, an emitter coupled to said second supply voltage terminal, and a base coupled to said second supply voltage terminal by said diode; a third transistor having a base coupled to receive a reference voltage, a collector coupled to said first supply voltage terminal by said second resistor, and an emitter coupled to said second supply voltage terminal by said third resistor; and a fourth transistor having a base coupled to said collector of said third transistor, a collector coupled to said first supply voltage terminal, and an emitter coupled to said base of said second transistor by said fourth resistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-16 | 1990-08-18 | 1991-02-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-16 | 1994-08-18 | 1995-02-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-16 | 1998-08-18 | 1999-02-17 | $7700.00 | Window Closed / Lapsed |