US4678942A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Emitter coupled logic circuit with high drivability for capacitive load
Assignee: Fujitsu Ltd
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Filing: 1985-09-23
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Granted: 1987-07-07
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Expires: 2005-09-23
Abstract
Abstract An ECL (Emitter Coupled Logic) circuit is provided which has an increased ability to drive a large capacitive load or to drive a large fan-out circuit, wherein the power consumption per gate is reduced. The output circuit of the ECL circuit is provided with an emitter follower transistor which has the current therethrough detected by a detecting transistor. A current control transistor is provided to quickly charge the load capacitance under the control of the detecting transistor, and thus, the voltage drop of the output signal is improved. One of the emitter follower transistor and the current transistor are always cut off when the other is in a conductive state, and therefore, the current running through the circuit is reduced.
Inventors
- 👤 Yasunori Kanai
- 👤 Taichi Saitoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:18
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/0136; H03K19/0008; H03K19/001; H03K19/02; H03K19/08; H03K19/082; H03K19/086
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
143 words
An emitter coupled logic (ECL) circuit comprising: at least a pair of transistors having the emitters thereof coupled together; an emitter follower transistor for providing an output, said emitter follower transistor having a base connected to the collector of one of said pair of transistors; an output terminal connected to the emitter of the emitter follower transistor; a current control transistor connected to the emitter follower transistor; and a control circuit means coupled to the collector of said emitter follower transistor for detecting the collector current of said emitter follower transistor, and said control circuit means being connected to the base of said current control transistor for controlling the current through said current control transistor in accordance with the collector current of the emitter follower transistor, so that said current control transistor pulls down the output voltage when the collector current becomes small.
Claim 2
Dependent Claim
143 words
An emitter coupled logic (ECL) circuit comprising: at least a pair of transistors having the emitters thereof coupled together; an emitter follower transistor for providing an output, said emitter follower transistor having a base connected to the collector of one of said pair of transistors; an output terminal connected to the emitter of the emitter follower transistor; a current control transistor connected to the emitter follower transistor; and a control circuit means coupled to the collector of said emitter follower transistor for detecting the collector current of said emitter follower transistor, and said control circuit means being connected to the base of said current control transistor for controlling the current through said current control transistor in accordance with the collector current of the emitter follower transistor, so that said current control transistor pulls down the output voltage when the collector current becomes small.
Claim 3
Dependent Claim
59 words
An ECL circuit according to claim 1, wherein said control circuit means comprises: a resistor connected between the collector of said emitter follower transistor and the positive side of a first voltage source; and a detecting means connected to the collector of said emitter follower transistor, wherein output of said detecting means is connected to said current control transistor.
Claim 4
Dependent Claim
21 words
An ECL circuit according to claim 2, wherein said detecting means is a pair of transistors connected as a Darlington pair.
Claim 5
Dependent Claim
41 words
An ECL circuit according to claim 2, including a resistor and a capacitor connected in parallel wherein the emitter of said current control transistor is connected to the negative side of a second voltage source through said parallel resistor and capacitor.
Claim 6
Dependent Claim
34 words
An ECL circuit according to claim 2, wherein said detecting means comprises a detecting transistor and a diode connected between the emitter of said detecting transistor and the base of said current control transistor.
Claim 7
Dependent Claim
62 words
An ECL circuit according to claim 2, wherein said control circuit means further comprises: a clamp diode connected between the collector of said emitter follower transistor and the positive side of said first voltage source; and wherein said detecting means comprises a detecting transistor and a level shift diode connected between said detecting transistor and the base of said current control transistor.
Claim 8
Dependent Claim
30 words
An ECL circuit according to claim 2, wherein said detecting means comprises a detecting transistor and a clamp diode connected between the base and the collector of said detecting transistor.
Claim 9
Dependent Claim
29 words
An ECL circuit according to claim 2, further comprising a resistor connected between the base of said current control transistor and the negative side of a second voltage source.
Claim 10
Dependent Claim
79 words
An ECL circuit according to claim 2, further comprising a series connected circuit comprising: a first resistor having one terminal connected to said detecting means; a transistor having the base thereof connected to the base of said current control transistor and the collector thereof connected to the other terminal of said first resistor and the base of said transistor; and a second resistor connected between the emitter of said transistor and the negative side of a second voltage source.
Claim 11
Dependent Claim
16 words
An ECL circuit according to claim 2, wherein all of said transistors are npn type transistors.
Claim 12
Dependent Claim
29 words
An ECL circuit according to claim 2, wherein said detecting means includes a detecting transistor and wherein said detecting transistor and said current control transistor are pnp type transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-06 | 1991-01-05 | 1991-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-06 | 1995-01-05 | 1995-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-06 | 1999-01-05 | 1999-07-07 | $7700.00 | Window Closed / Lapsed |