US4687953A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic ECL line driver circuit
Assignee: RPX Corp
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Filing: 1986-04-18
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Granted: 1987-08-18
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Expires: 2006-04-18
Abstract
Abstract A dynamic ECL line driver circuit for driving line loads having significant capacitance which includes an input transistor, a reference transistor, a main current source transistor and an emitter follower transistor. The line driver circuit further includes a dynamic current enhancement circuit formed of a buffer portion, a current enhancement portion and a dynamic charge pumping portion. The current enhancement portion includes a current source enhancement transistor and the dynamic charge pumping portion includes a capacitor. The buffer portion is utilized for amplifying and inverting a transient voltage at the collector of the reference transistor. One end of the capacitor is connected to the collector of the reference transistor and the base of the emitter follower transistor, and the other end thereof is coupled to the base of the current source enhancement transistor via the buffer portion. As logic transitions occur at the base of the emitter follower transistor, the transient voltage is impressed upon the base of the current source enhancement transistor so as to speed up the transitions on an output terminal.
Inventors
- 👤 Hemmige D. Varadarajan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:29
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/0136; H03K19/02; H03K19/08; H03K19/082; H03K19/086
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
394 words
An ECL line driver circuit for driving line loads having significant capacitance comprising: an input transistor having its collector coupled to a supply potential and its base connected to receive an input logic signal; a reference transistor having its collector connected to the supply potential via a load resistor, its base connected to a bias voltage, and its emitter connected to the emitter of said input transistor; a main current source transistor having its collector connected to the common emitters of said input transistor and said reference transistor, its base connected to a reference voltage, and its emitter connected to a ground potential via an emitter resistor; an emitter follower transistor having its collector connected to the supply potential, its base connected to the collector of either said input or reference transistor, and its emitter connected to an output terminal; buffer means formed of a first transistor and a second transistor for amplifying and inverting a transient voltage at the collector of said input or reference transistor, said first transistor having its collector connected to the emitter of said emitter follower transistor, its base connected to the reference voltage and its emitter connected to the emitter of said second transistor, said second transistor having its collector connected to a first end of a first resistor and its base connected to a first end of a second resistor, the second end of said second resistor being connected to the first end of said first resistor, the second end of said first resistor being connected to the emitter of said emitter follower transistor, the common emitters of said first and second transistors being connected to the ground potential via a third resistor; a current source enhancement transistor having its collector connected to the emitter of said emitter follower transistor and to the output terminal, its base connected to said second end of said second resistor and its emitter connected to the ground potential via a fourth resistor; and a capacitor having its one end connected to the collector of said input or reference transistor and its other end connected to the base of said second transistor of said buffer means whereby the transient voltage is impressed upon said base of said current source enhancement transistor during logic level transitions at the base of the emitter follower transistor to speed up said transitions on said output terminal.
Claim 2
Dependent Claim
394 words
An ECL line driver circuit for driving line loads having significant capacitance comprising: an input transistor having its collector coupled to a supply potential and its base connected to receive an input logic signal; a reference transistor having its collector connected to the supply potential via a load resistor, its base connected to a bias voltage, and its emitter connected to the emitter of said input transistor; a main current source transistor having its collector connected to the common emitters of said input transistor and said reference transistor, its base connected to a reference voltage, and its emitter connected to a ground potential via an emitter resistor; an emitter follower transistor having its collector connected to the supply potential, its base connected to the collector of either said input or reference transistor, and its emitter connected to an output terminal; buffer means formed of a first transistor and a second transistor for amplifying and inverting a transient voltage at the collector of said input or reference transistor, said first transistor having its collector connected to the emitter of said emitter follower transistor, its base connected to the reference voltage and its emitter connected to the emitter of said second transistor, said second transistor having its collector connected to a first end of a first resistor and its base connected to a first end of a second resistor, the second end of said second resistor being connected to the first end of said first resistor, the second end of said first resistor being connected to the emitter of said emitter follower transistor, the common emitters of said first and second transistors being connected to the ground potential via a third resistor; a current source enhancement transistor having its collector connected to the emitter of said emitter follower transistor and to the output terminal, its base connected to said second end of said second resistor and its emitter connected to the ground potential via a fourth resistor; and a capacitor having its one end connected to the collector of said input or reference transistor and its other end connected to the base of said second transistor of said buffer means whereby the transient voltage is impressed upon said base of said current source enhancement transistor during logic level transitions at the base of the emitter follower transistor to speed up said transitions on said output terminal.
Claim 3
Dependent Claim
28 words
A line driver circuit as claimed in claim 1, further comprising a load current source connected between the emitter of said emitter follower transistor and the ground potential.
Claim 4
Dependent Claim
66 words
A line driver circuit as claimed in claim 2, wherein said load current source is formed of a current source transistor and an fifth resistor, said load current source transistor having its collector connected to the emitter of said emitter follower transistor, its base coupled to the emitter of said current source enhancement transistor and its emitter connected to the ground potential via said fifth resistor.
Claim 5
Dependent Claim
323 words
An ECL line driver circuit for driving line loads having significant capacitance comprising: an input transistor having its collector connected to a supply potential and its base connected to receive an input logic signal; a reference transistor having its collector connected to the supply potential via a load resistor, its base connected to a bias voltage, and its emitter connected to the emitter of said input transistor; a main current source transistor having its collector connected to the common emitters of said input transistor and said reference transistor, its base connected to a reference valtage, and its emitter connected to a ground potential via an emitter resistor; an emitter follower transistor having its collector connected to the supply potential, its base connected to the collector of said reference transistor, and its emitter connected to an output terminal; dynamic current enhancement means responsive to a transient signal at the collector of said reference transistor for reducing the propagation delay at said output terminal; and said dynamic current enhancement means including buffer means formed of a first transistor and a second transistor for amplifying and inverting a transient voltage at the collector of said reference transistor, said first transistor having its collector connected to the emitter of said emitter follower transistor, its base connected to the reference voltage and its emitter connected to the emitter of said second transistor, said second transistor having its collector connected to a first end of a first resistor and its base connected to a first end of a second resistor, the base of said second transistor being further coupled to the collector of said reference transistor, the second end of said second resistor being connected to the first end of said first resistor, the second end of said first resistor being connected to the emitter of said emitter follower transistor, the common emitters of said first and second transistors being connected to the ground potential via a third resistor.
Claim 6
Dependent Claim
323 words
An ECL line driver circuit for driving line loads having significant capacitance comprising: an input transistor having its collector connected to a supply potential and its base connected to receive an input logic signal; a reference transistor having its collector connected to the supply potential via a load resistor, its base connected to a bias voltage, and its emitter connected to the emitter of said input transistor; a main current source transistor having its collector connected to the common emitters of said input transistor and said reference transistor, its base connected to a reference valtage, and its emitter connected to a ground potential via an emitter resistor; an emitter follower transistor having its collector connected to the supply potential, its base connected to the collector of said reference transistor, and its emitter connected to an output terminal; dynamic current enhancement means responsive to a transient signal at the collector of said reference transistor for reducing the propagation delay at said output terminal; and said dynamic current enhancement means including buffer means formed of a first transistor and a second transistor for amplifying and inverting a transient voltage at the collector of said reference transistor, said first transistor having its collector connected to the emitter of said emitter follower transistor, its base connected to the reference voltage and its emitter connected to the emitter of said second transistor, said second transistor having its collector connected to a first end of a first resistor and its base connected to a first end of a second resistor, the base of said second transistor being further coupled to the collector of said reference transistor, the second end of said second resistor being connected to the first end of said first resistor, the second end of said first resistor being connected to the emitter of said emitter follower transistor, the common emitters of said first and second transistors being connected to the ground potential via a third resistor.
Claim 7
Dependent Claim
62 words
A line driver circuit as claimed in claim 4, wherein said dynamic current enhancement means further includes a current source enhancement transistor having its collector connected to the emitter of said emitter follower transistor and to the output terminal, its base connected to the second end of said second resistor and its emitter connected to the ground potential via a fourth resistor.
Claim 8
Dependent Claim
54 words
A line driver circuit as claimed in claim 5, wherein said dynamic current enhancement means further includes dynamic charge pumping means formed of a capacitor, one end of the capacitor being connected to the collector of said reference transistor, the other end of the capacitor being connected to the base of said second transistor.
Claim 9
Dependent Claim
28 words
A line driver circuit as claimed in claim 6, further comprising a load current source connected between the emitter of said emitter follower transistor and the ground potential.
Claim 10
Dependent Claim
67 words
A line driver circuit as claimed in claim 7, wherein said load current source is formed of a load current source transistor and a fifth resistor, said load current source transistor having its collector connected to the emitter of said emitter follower transistor, its base coupled to the emitter of said current source enhancement transistor and its emitter connected to the ground potential via said fifth resistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-17 | 1991-02-16 | 1991-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-17 | 1995-02-16 | 1995-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-17 | 1999-02-16 | 1999-08-18 | $7700.00 | Window Closed / Lapsed |