Method of manufacturing resin-encapsulated semiconductor device package using photoresist or pre-peg lead frame dam bars

Claim 1

A method for manufacturing a semiconductor device package comprising: providing a patterned lead frame of an electrically conductive material including a plurality of electrically conductive leads having inner lead portions and outer lead portions; mounting a semiconductor chip within said patterned lead frame in proximity to said inner lead portions; connecting electrically conductive connector wires between said semiconductor chip and at least some of said inner lead portions; applying nonconductive photoresist material onto said lead frame overlying local predetermined areas of the adjacent outer lead portions by disposing the photoresist material locally in registration with said predetermined areas of the adjacent outer lead portions; applying pressure to said photoresist material in a direction forcing portions of said photoresist material into the spaces between adjacent outer lead portions; filling the spaces between the localized predetermined areas of the adjacent outer lead portions with portions of said photoresist material in response to the application of pressure thereto, thereby embedding the local predetermined areas of the adjacent outer lead portions with photoresist material and forming elongated bars of said photoresist material in the localized predetermined areas of the adjacent outer lead portions; encapsulating said semiconductor chip, said connector wires and portions of said plurality of electrically conductive leads other than said outer lead portions in a molded mass of nonconductive material; and blocking the outflow of the mass of nonconductive material along the spaces between adjacent outer lead portions by the photoresist material embedded in the spaces between adjacent outer lead portions during the encapsulation of said semiconductor chip, said connector wires and portions of said plurality of electrically conductive leads other than said outer lead portions by said molded mass of nonconductive material, thereby ensuring hermetic sealing by the molded mass of nonconductive material with respect to the semiconductor chip, said connector wires and the plurality of electrically conductive leads of said lead frame.

Claim 2

A method for manufacturing a semiconductor device package comprising: providing a patterned lead frame of an electrically conductive material including a plurality of electrically conductive leads having inner lead portions and outer lead portions; mounting a semiconductor chip within said patterned lead frame in proximity to said inner lead portions; connecting electrically conductive connector wires between said semiconductor chip and at least some of said inner lead portions; applying nonconductive photoresist material onto said lead frame overlying local predetermined areas of the adjacent outer lead portions by disposing the photoresist material locally in registration with said predetermined areas of the adjacent outer lead portions; applying pressure to said photoresist material in a direction forcing portions of said photoresist material into the spaces between adjacent outer lead portions; filling the spaces between the localized predetermined areas of the adjacent outer lead portions with portions of said photoresist material in response to the application of pressure thereto, thereby embedding the local predetermined areas of the adjacent outer lead portions with photoresist material and forming elongated bars of said photoresist material in the localized predetermined areas of the adjacent outer lead portions; encapsulating said semiconductor chip, said connector wires and portions of said plurality of electrically conductive leads other than said outer lead portions in a molded mass of nonconductive material; and blocking the outflow of the mass of nonconductive material along the spaces between adjacent outer lead portions by the photoresist material embedded in the spaces between adjacent outer lead portions during the encapsulation of said semiconductor chip, said connector wires and portions of said plurality of electrically conductive leads other than said outer lead portions by said molded mass of nonconductive material, thereby ensuring hermetic sealing by the molded mass of nonconductive material with respect to the semiconductor chip, said connector wires and the plurality of electrically conductive leads of said lead frame.

Claim 3

A method for manufacturing a semiconductor device package comprising: providing a patterned lead frame of an electrically conductive material including a plurality of electrically conductive leads having inner lead portions and outer lead portions; mounting a semiconductor chip within said patterned lead frame in proximity to said inner lead portions; connecting electrically conductive connector wires between said semiconductor chip and at least some of said inner lead portions; positioning a layer of nonconductive prepreg material on said lead frame overlying local predetermined areas of the adjacent outer lead portions of said lead frame; disposing the prepreg material locally in registration with said predetermined areas of the adjacent outer lead portions; applying pressure to said layer of nonconductive prepreg material in a direction forcing portions of said layer of nonconductive prepreg material into the spaces between adjacent outer lead portions; filling the spaces between the localized predetermined areas of the adjacent outer lead portions with portions of said nonconductive prepreg material in response to the application of pressure thereto, thereby embedding the local predetermined areas of the adjacent outer lead portions with nonconductive prepreg material and forming elongated bars of said nonconductive prepreg material in the localized predetermined areas of the adjacent outer lead portions; encapsulating said semiconductor chip, said connector wires and portions of said plurality of electrically conductive leads other than said outer lead portions in a molded mass of nonconductive material; and blocking the outflow of the mass of nonconductive material along the spaces between adjacent outer lead portions by the nonconductive prepreg material embedded in the spaces between adjacent outer lead portions during the encapsulation of said semiconductor chip, said connector wires and portions of said plurality of electrically conductive leads other than said outer lead portions by said molded mass of nonconductive material, thereby ensuring hermetic sealing by the molded mass of nonconductive material with respect to the semiconductor chip, said connector wires and the plurality of electrically conductive leads of said lead frame.

Claim 4

A method for manufacturing a semiconductor device package comprising: providing a patterned lead frame of an electrically conductive material including a plurality of electrically conductive leads having inner lead portions and outer lead portions; mounting a semiconductor chip within said patterned lead frame in proximity to said inner lead portions; connecting electrically conductive connector wires between said semiconductor chip and at least some of said inner lead portions; positioning a layer of nonconductive prepreg material on said lead frame overlying local predetermined areas of the adjacent outer lead portions of said lead frame; disposing the prepreg material locally in registration with said predetermined areas of the adjacent outer lead portions; applying pressure to said layer of nonconductive prepreg material in a direction forcing portions of said layer of nonconductive prepreg material into the spaces between adjacent outer lead portions; filling the spaces between the localized predetermined areas of the adjacent outer lead portions with portions of said nonconductive prepreg material in response to the application of pressure thereto, thereby embedding the local predetermined areas of the adjacent outer lead portions with nonconductive prepreg material and forming elongated bars of said nonconductive prepreg material in the localized predetermined areas of the adjacent outer lead portions; encapsulating said semiconductor chip, said connector wires and portions of said plurality of electrically conductive leads other than said outer lead portions in a molded mass of nonconductive material; and blocking the outflow of the mass of nonconductive material along the spaces between adjacent outer lead portions by the nonconductive prepreg material embedded in the spaces between adjacent outer lead portions during the encapsulation of said semiconductor chip, said connector wires and portions of said plurality of electrically conductive leads other than said outer lead portions by said molded mass of nonconductive material, thereby ensuring hermetic sealing by the molded mass of nonconductive material with respect to the semiconductor chip, said connector wires and the plurality of electrically conductive leads of said lead frame.