Patent US5254880A successfully refreshed from Google Patents.
US5254880A
Expired / Lapsed
US
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Large scale integrated circuit having low internal operating voltage
Assignee: Hitachi Ltd
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Filing: 1992-04-03
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Granted: 1993-10-19
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Expires: 2012-04-03
Abstract
Abstract Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.
Inventors
- 👤 Masashi Horiguchi
- 👤 Masakazu Aoki
- 👤 Kiyoo Itoh
- 👤 Yoshinobu Nakagome
- 👤 Norio Miyake
- 👤 Takaaki Noda
- 👤 Jun Etoh
- 👤 Hitoshi Tanaka
- 👤 Shin ichi Ikenaga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:36
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/462; G05F1/465; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G05F3/242; G05F3/245; G05F3/247; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G11C5/00; G11C5/14; G11C5/147; H; H10; H10D; H10D89/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
189 words
A semiconductor device comprising: an internal voltage generator generating an internal voltage different from an external voltage; a first memory array; a second memory array; a first pulse generator using said internal voltage as a power supply and supplying a pulse to said first memory array; a second pulse generator using said internal voltage as a power supply and supplying a pulse to said second memory array; wherein said first pulse generator is supplied with a current from said internal voltage generator and outputs a pulse, when a first address signal is supplied to said first pulse generator; said second pulse generator is supplied with a current from said internal voltage generator and outputs a pulse, when a second address signal is supplied to said second pulse generator; said first pulse generator is not supplied with a current from said internal voltage generator while said second pulse generator is supplied with a current from said internal voltage generator; and said second pulse generator is not supplied with a current from said internal voltage generator while said first pulse generator is supplied with a current from said internal voltage generator.
Claim 2
Dependent Claim
189 words
A semiconductor device comprising: an internal voltage generator generating an internal voltage different from an external voltage; a first memory array; a second memory array; a first pulse generator using said internal voltage as a power supply and supplying a pulse to said first memory array; a second pulse generator using said internal voltage as a power supply and supplying a pulse to said second memory array; wherein said first pulse generator is supplied with a current from said internal voltage generator and outputs a pulse, when a first address signal is supplied to said first pulse generator; said second pulse generator is supplied with a current from said internal voltage generator and outputs a pulse, when a second address signal is supplied to said second pulse generator; said first pulse generator is not supplied with a current from said internal voltage generator while said second pulse generator is supplied with a current from said internal voltage generator; and said second pulse generator is not supplied with a current from said internal voltage generator while said first pulse generator is supplied with a current from said internal voltage generator.
Claim 3
Dependent Claim
161 words
A semiconductor device comprising: an internal voltage generator generating an internal voltage different from an external voltage; a first memory array; a second memory array; a first pulse generator means for selectively supplying a first pulse to said first memory array using said internal voltage as a power supply, the first pulse generator means including means for supplying current from said internal voltage generator and means for outputting the first pulse when a first address signal is supplied thereto; a second pulse generator means for selectively supplying a second pulse to said second memory array using said internal voltage as a power supply, the second pulse generator means including means for supplying current from said internal voltage generator and means for outputting the second pulse when a second address signal is supplied thereto; discriminator means for enabling supply of a selected one of said first pulse generator and said second pulse generator current from said internal voltage generator at one time.
Claim 4
Dependent Claim
161 words
A semiconductor device comprising: an internal voltage generator generating an internal voltage different from an external voltage; a first memory array; a second memory array; a first pulse generator means for selectively supplying a first pulse to said first memory array using said internal voltage as a power supply, the first pulse generator means including means for supplying current from said internal voltage generator and means for outputting the first pulse when a first address signal is supplied thereto; a second pulse generator means for selectively supplying a second pulse to said second memory array using said internal voltage as a power supply, the second pulse generator means including means for supplying current from said internal voltage generator and means for outputting the second pulse when a second address signal is supplied thereto; discriminator means for enabling supply of a selected one of said first pulse generator and said second pulse generator current from said internal voltage generator at one time.
Claim 5
Dependent Claim
44 words
The semiconductor device of claim 2 wherein the discriminator means includes means for enabling supply of the selected one of said first pulse generator and said second pulse generator currents in accordance with application of the first address signal and the second address signal.
Claim 6
Dependent Claim
57 words
The semiconductor device of claim 3 wherein the discriminator means further includes means for enabling supply of the selected one of said first pulse generator and said second pulse generator currents in accordance with application of the first address signal and the second address signal, both address signals being formed in an inverse relation with one another.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-10-18 | 1997-04-19 | 1997-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-18 | 2001-04-19 | 2001-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-10-18 | 2005-04-19 | 2005-10-19 | $7700.00 | Window Closed / Lapsed |