Patent US5253202A successfully refreshed from Google Patents.
US5253202A
Expired / Lapsed
US
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Word line driver circuit for dynamic random access memories
Assignee: International Business Machines Corp
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Filing: 1991-02-05
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Granted: 1993-10-12
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Expires: 2011-02-05
Abstract
Abstract A wordline driver circuit for reading the contents of a Dynamic Random Access Memory (DRAM). The circuit is implemented in CMOS and is capable of pulling the wordlines to a negative potential with respect to the substrate, thereby decreasing the access time. An NMOS pull-down transistor channel is implemented as a P-well within an N-well. Applying a negative potential to the source of the pull-down transistor permits the transistor to be switched so that a negative potential is applied to the wordline when the NMOS pull-down transistor is gated into conduction. A PMOS pull-up transistor is serially connected to the NMOS pull-down transistor drain, permitting the wordline to be driven positively.
Inventors
- 👤 Gary B. Bronner
- 👤 Sang H. Dhong
- 👤 Wei Hwang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:28
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4085; G11C11/4087
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
160 words
A wordline driver for a CMOS dynamic random access memory comprising: a PMOS transistor having a source connected to a positive terminal of a voltage source serially connected with an NMOS transistor, said PMOS and NMOS transistor having a common gate connection for receiving a decoder logic signal, and having a common series connection for driving the word line of a row of memory cells; a trench capacitor connected at one end to said NMOS transistor drain and connected at a second end to a common substrate which is connected to a negative terminal of said voltage source; and, an on-chip voltage generator connected to said one end of said trench capacitor and said substrate for charging said trench capacitor to a potential below the potential of said substrate, whereby said wordline is driven between a positive potential applied to said PMOS transistor source and a negative voltage supplied by said trench capacitor in response to said decoder logic signal.
Claim 2
Dependent Claim
160 words
A wordline driver for a CMOS dynamic random access memory comprising: a PMOS transistor having a source connected to a positive terminal of a voltage source serially connected with an NMOS transistor, said PMOS and NMOS transistor having a common gate connection for receiving a decoder logic signal, and having a common series connection for driving the word line of a row of memory cells; a trench capacitor connected at one end to said NMOS transistor drain and connected at a second end to a common substrate which is connected to a negative terminal of said voltage source; and, an on-chip voltage generator connected to said one end of said trench capacitor and said substrate for charging said trench capacitor to a potential below the potential of said substrate, whereby said wordline is driven between a positive potential applied to said PMOS transistor source and a negative voltage supplied by said trench capacitor in response to said decoder logic signal.
Claim 3
Dependent Claim
26 words
The wordline driver of claim 1, wherein said NMOS transistor is implemented as a P-well forming a conductive channel in an N-well of a P+ substrate.
Claim 4
Dependent Claim
15 words
The wordline driver of claim 1 wherein said trench capacitor is formed in said substrate.
Claim 5
Dependent Claim
69 words
The wordline driver of claim 1 wherein said on-chip voltage generator comprises: a ring oscillator for supplying an alternating pulsed signal; a clamping circuit connecting said ring oscillator to said trench capacitor, charging said trench capacitor to a negative voltage with respect to said substrate; and, a voltage regulator connected to monitor said trench capacitor voltage and inhibit said ring oscillator when said capacitor has reached a predetermined level.
Claim 6
Dependent Claim
58 words
The wordline driver of claim 4 wherein said voltage regulator comprises a cross coupled latch, having two nodes, one of which is connected through a transistor to a source of potential VDD, the other of which is connected through a transistor to a reference source of potential, said second transistor having a gate connected to said trench capacitor.
Claim 7
Dependent Claim
77 words
The wordline driver of claim 1 further comprising: a second PMOS transistor serially connected to a second NMOS transistor, said second transistors forming common gate connections connected to receive said decoder signal, and having a serial connection connected to gate connections of said first PMOS and NMOS serially connected transistors, said second serially connected transistors providing a regulating function when said decoder signal amplitude is greater than the power supply voltage across said first serially connected transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-10-11 | 1997-04-12 | 1997-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-11 | 2001-04-12 | 2001-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-10-11 | 2005-04-12 | 2005-10-12 | $7700.00 | Window Closed / Lapsed |