Positively biased substrate IC with thermal oxide guard ring

Claim 2

In an integrated circuit having a substrate at a predetermined positive potential, a first layer of thermally grown insulation over and in contact with said substrate, a second layer of low moisture resistant, chemically vapor deposited insulation including hydrogen ions formed over and in contact with said first layer, aluminum interconnects including at least one aluminum interconnect at a predetermined negative potential over and in contact with said first layer, spaced from the lateral edge of said first layer and separated from the said lateral edge by said second layer, and a current path between said interconnect at said negative potential and said substrate through said second layer, the improvement comprising said first layer extends laterally across the substrate in all directions a distance sufficiently greater than said second layer to prevent said current path between the interconnect at said negative potential and said substrate through said second layer.

Claim 3

The integrated circuit of claim 1 wherein said first layer extends at least 0.05 mils per volt of potential difference between said predetermined positive and negative potentials.

Claim 4

The integrated circuit of claim 1 wherein said first layer is silicon dioxide and has a resistance of at least 10 9 ohms.

Claim 5

The integrated circuit of claim 1 wherein said second layer is phosphorus doped siloxane.

Claim 6

The integrated circuit of claim 1 wherein said circuit includes a complementary pair of insulated gate field effect transistors and said substrate is N conductivity type.

Claim 7

In a wafer having a plurality of integrated circuits to be separated at scribe lines, a first layer of thermally grown insulation over and in contact with a substrate, a second layer of chemically vapor-deposited insulation including hydrogen ions formed over and in contact with said first layer, aluminum interconnects over and in contact with said first layer including a first interconnect means in contact with said substrate for applying a predetermined positive potential to said substrate and a second interconnect means for applying a predetermined negative potential to said integrated circuit spaced from the lateral edge of said first layer and separated therefrom by said second layer through which a current path can be defined between said second interconnect means and said substrate, the improvement comprising said first layer is discontinuous at said scribe lines and said second layer being recessed from said edge of said first layer at least 0.05 mils per volt of potential difference between said predetermined positive and negative potentials.

Claim 8

In a wafer having a plurality of integrated circuits to be separated at scribe lines, a first layer of thermally grown insulation over and in contact with a substrate, a second layer of chemically vapor-deposited insulation including hydrogen ions formed over and in contact with said first layer, aluminum interconnects over and in contact with said first layer including a first interconnect means in contact with said substrate for applying a predetermined positive potential to said substrate and a second interconnect means for applying a predetermined negative potential to said integrated circuit spaced from the lateral edge of said first layer and separated therefrom by said second layer through which a current path can be defined between said second interconnect means and said substrate, the improvement comprising said first layer is discontinuous at said scribe lines and said second layer being recessed from said edge of said first layer at least 0.05 mils per volt of potential difference between said predetermined positive and negative potentials.

Claim 9

In a wafer having a plurality of integrated circuits to be separated at scribe lines, a first layer of thermally grown insulation over and in contact with a substrate, a second layer of low moisture resistant insulation including hydrogen ions formed over and in contact with said first layer, aluminum interconnects over and in contact with said first layer including a first interconnect means in contact with said substrate for applying a predetermined positive potential to said substrate and a second interconnect means for applying a predetermined negative potential to said integrated circuit spaced from the lateral edge of said first layer and separated therefrom by said second layer through which a current path can be defined between said second interconnect means and said substrate, the improvement comprising said first layer is discontinuous at said scribe lines and said second layer being recessed from said edge of said first layer a distance sufficient to prevent said current path between said second aluminum interconnect means and the substrate through said second layer.

Claim 10

In a wafer having a plurality of integrated circuits to be separated at scribe lines, a first layer of thermally grown insulation over and in contact with a substrate, a second layer of low moisture resistant insulation including hydrogen ions formed over and in contact with said first layer, aluminum interconnects over and in contact with said first layer including a first interconnect means in contact with said substrate for applying a predetermined positive potential to said substrate and a second interconnect means for applying a predetermined negative potential to said integrated circuit spaced from the lateral edge of said first layer and separated therefrom by said second layer through which a current path can be defined between said second interconnect means and said substrate, the improvement comprising said first layer is discontinuous at said scribe lines and said second layer being recessed from said edge of said first layer a distance sufficient to prevent said current path between said second aluminum interconnect means and the substrate through said second layer.

Claim 11

The wafer of claim 7 wherein said second layer is recessed from the edge of said first layer at least 0.05 mils per volt of potential difference between said predetermined positive and negative potentials.

Claim 12

The wafer of claim 7 wherein said first layer of silicon dioxide and has a resistance of at least 10 9 ohms.

Claim 13

The wafer of claim 7 wherein said second layer is phosphorus doped siloxane.

Claim 14

The wafer of claim 7 wherein said circuit includes a pair of complementary metal oxide semiconductor transistors and said substrate is N conductivity type.

Claim 15

In an integrated circuit having a substrate at a predetermined positive potential, a first layer of thermally grown insulation on said substrate, a second layer of chemically vapor-deposited insulation including hydrogen ions formed over and in contact with said first layer, aluminum interconnects including at least one aluminum interconnect at a predetermined negative potential over and in contact with said first layer, spaced from the lateral edge of said first layer and separated from said lateral edge by said second layer, and a current path between said interconnect at said negative potential and said substrate through said second layer, the improvement comprising the first layer extends laterally across the substrate in all directions a greater distance than said second layer at least 0.05 mils per volt of potential difference between said predetermined positive and negative potentials.

Claim 16

In an integrated circuit having a substrate at a predetermined positive potential, a first layer of thermally grown insulation on said substrate, a second layer of chemically vapor-deposited insulation including hydrogen ions formed over and in contact with said first layer, aluminum interconnects including at least one aluminum interconnect at a predetermined negative potential over and in contact with said first layer, spaced from the lateral edge of said first layer and separated from said lateral edge by said second layer, and a current path between said interconnect at said negative potential and said substrate through said second layer, the improvement comprising the first layer extends laterally across the substrate in all directions a greater distance than said second layer at least 0.05 mils per volt of potential difference between said predetermined positive and negative potentials.

Claim 17

The integrated circuit of claim 12 wherein said second layer is phosphorus doped silicon oxide.