Multichip integrated circuit modules

Claim 2

A multichip integrated circuit package comprising: a substrate having a flat upper surface; a plurality of unpackaged integrated circuit chips disposed above said substrate's flat upper surface, said integrated circuit chips each being spaced apart from the other of said integrated circuit chips and each having at least one interconnection pad on a top surface thereof, the top surfaces of said integrated circuit chips being in a plane substantially parallel to said substrate's flat upper surface, said integrated circuit chips also each having at least one side surface; an encapsulant surrounding said integrated circuit chips including said top surfaces and said at least one side surfaces thereof and completely filling all space between adjacent integrated circuit chips disposed above said substrate's flat upper surface, said encapsulant having an upper surface above the tops of the integrated circuit chips and having a plurality of via openings therein, said openings being aligned with at least some of said interconnection pads; and a pattern of interconnection conductors disposed within at least some of said plurality of via openings and above the upper surface of said encapsulant so as to extend between said at least some of said plurality of via openings, and so as to provide direct electrical connection to at least some of said interconnection pads through said openings, wherein a unitary package of multiple directly interconnected integrated circuit chips is produced.

Claim 3

The integrated circuit package of claim 1, wherein said encapsulant comprises a polymer.

Claim 4

The integrated circuit package of claim 2, wherein said encapsulant is selected from the group consisting of thermoplastic and thermoset materials.

Claim 5

The integrated circuit package of claim 1, wherein the substrate comprises material selected from the group consisting of glass, metal, ceramic, plastic, silicon and composites.

Claim 6

The integrated circuit package of claim 1, wherein the substrate comprises alumina.

Claim 7

The integrated circuit package of claim 1, further including: a dielectric layer overlying said encapsulant and said interconnection conductors, said dielectric layer also including a plurality of via openings therein aligned with at least some of said interconnection conductors disposed on said encapsulant; and a second plurality of interconnection conductors disposed above said dielectric layer and extending between at least some of the openings in said dielectric layer so as to provide electrical connection with interconnection pattern conductors disposed above said encapsulant.

Claim 8

The integrated circuit package of claim 6, wherein said dielectric layer, together with said second plurality of interconnection conductors, is removable.

Claim 9

The integrated circuit package of claim 7, wherein said dielectric layer comprises a solvent-sensitive layer.

Claim 10

The integrated circuit package of claim 1, further including: a solvent-sensitive layer overlying said encapsulant and said interconnection conductors; a dielectric layer overlying said solvent-sensitive layer, said dielectric layer and said solvent-sensitive layer including a plurality of via openings therein aligned with at least some of said interconnection pattern conductors disposed on said encapsulant; and a second plurality of interconnection conductors disposed above said dielectric layer and extending between at least some of the openings in said dielectric layer so as to provide electrical connection with interconnection pattern conductors disposed on said encapsulant.

Claim 11

The integrated circuit package of claim 1, further comprising: at least one preprocessed chip disposed on said substrate's flat upper surface; and wherein: said encapsulant overlies said preprocessed chip, said encapsulant having a via opening therein to the upper surface of said preprocessed chip; and said pattern of interconnection conductors is disposed above the upper surface of said encapsulant so as to extend between at least some of said via openings, including said opening over the upper surface of said preprocessed chip, so as to provide electrical connection to at least some of said integrated circuit chips and said preprocessed chip.

Claim 12

The integrated circuit package of claim 10, wherein said preprocessed chip is positioned near an edge of said multichip package and comprises an input output circuit.

Claim 13

The integrated circuit package of claim 10, wherein said preprocessed chip includes a series of conductive lands on a top surface thereof for wire bonding thereto, and wherein said encapsulant overlies only a portion of the top surface of said preprocessed chip and a portion of said conductive lands located thereon, said encapsulant having a via opening therein over at least one of said series of conductive lands, said pattern of interconnection conductors being disposed above the upper surface of said encapsulant so as to extend between at least some of said via openings, including said via opening over said at least one land of said preprocessed chip, to provide electrical connection to at least some of said plurality of integrated circuit chips and said preprocessed chip.

Claim 14

The integrated circuit package of claim 10, wherein said preprocessed chip comprises a tiered power and ground bussing structure, said bussing structure including a power strip and a ground strip, and wherein said encapsulant overlies said power and ground bussing structure and has at least one via opening therein to each of said power and ground strips, said pattern of interconnection conductors being disposed above the upper surface of said encapsulant so as to provide electrical connection between said power and ground strips of said preprocessed chip and at least some of said integrated circuit chips.

Claim 15

The integrated circuit package of claim 10, wherein said preprocessed chip comprises a termination resistor, said resistor having pads on the upper surface thereof, and wherein said encapsulant's via openings and said pattern of interconnection conductors are disposed to provide electrical connection to said termination resistor and at least some of said integrated circuit chips.

Claim 16

The integrated circuit package of claim 10, wherein an adhesive layer is disposed on said substrate's flat upper surface between said plurality of integrated circuit chips and said substrate.

Claim 17

The integrated circuit package of claim 1, wherein an adhesive layer is disposed on said substrate's flat upper surface between said plurality of integrated circuit chips and said substrate, and further comprising a termination resistor array, said resistor array being disposed between said substrate and said adhesive layer, and wherein said adhesive layer has via openings therein aligned with selected ones of said plurality of via openings in said encapsulant and with selected electrical contact points in said termination resistor array.

Claim 18

The integrated circuit package of claim 16, wherein each termination resistor array is positioned below one of said plurality of integrated circuit chips.

Claim 19

The integrated circuit package of claim 1, further comprising an array of electrical contact pads on an upper surface of said package, said array of contact pads being electrically coupled via at least one level of interconnection conductors to at least some of said integrated circuit interconnection pads.

Claim 20

The integrated circuit package of claim 18, wherein said array of electrical contact pads on the upper surface of said package provide electrical interface to circuitry external to said package, and wherein said substrate has a lower surface, said lower substrate surface providing a thermal interface for dissipation of heat generated by said integrated circuit chips.

Claim 21

The integrated circuit package of claim 19, wherein said substrate's lower surface comprises a lower surface of said integrated circuit package.

Claim 22

The integrated circuit package of claim 1, wherein said upper surface of said encapsulant is flat and approximately 1-2 mils from the top surface of said integrated circuit chips.

Claim 23

The integrated circuit package of claim 1, wherein a thin continuous adhesive film is disposed on said substrate's flat upper surface between said plurality of integrated circuit chips and said substrate.

Claim 24

The integrated circuit package of claim 1, wherein said plurality of integrated circuit chips each have a predetermined thickness, said predetermined thickness being in the range of 4 mils to 8 mils.

Claim 25

The integrated circuit package of claim 18, wherein said array of electrical contact pads on the upper surface of said package substantially covers said package's upper surface, at least some of said array of contact pads being disposed over other than said plurality of integrated circuit chips.

Claim 26

The integrated circuit package of claim 1, further comprising: a signal plane disposed above the top surfaces of said plurality of integrated circuit chips; and a substantially uninterrupted conductive plane also disposed above the top surfaces of said integrated circuit chips, said substantially uninterrupted conductive plane being substantially parallel to said signal plane.

Claim 27

The integrated circuit package of claim 25, further comprising: at least one termination resistor disposed on the upper surface of said substrate; and connection means for coupling said signal plane to said at least one termination resistor.

Claim 28

The integrated circuit package of claim 1, wherein at least two substantially uninterrupted conductive planes are disposed above the top surfaces of said integrated circuit chips, each of said conductive planes being substantially parallel to said signal plane.

Claim 29

The integrated circuit package of claim 27, wherein one of said conductive planes comprises a ground plane and one of said conductive planes comprises a power plane.

Claim 30

The integrated circuit package of claim 28, wherein each chip of said plurality of integrated circuit chips has a predetermined thickness, said predetermined thickness being in the range of 4 mils to 8 mils.

Claim 31

The integrated circuit package of claim 28, wherein said ground plane is disposed between said signal plane and the top surfaces of said integrated circuit chips.

Claim 32

The integrated circuit package of claim 28, wherein said ground plane and said power plane are disposed in close, parallel opposing relation to each other, and further comprising a dielectric material disposed between said power plane and said conductive plane.

Claim 33

The integrated circuit package of claim 31, wherein said signal plane is spaced a distance y from the top surfaces of said integrated circuit chips and wherein said power plane is spaced a distance x from said ground plane, distance y being greater than distance x.

Claim 34

Multichip integrated circuit package comprising: a circuit component, said component having an upper surface with at least one interconnection pad thereon; a substrate having an upper surface and a lower surface, said substrate including a hole therein extending from said upper substrate surface to said lower substrate surface, said substrate hole being sized to accommodate said circuit component therein; at least one integrated circuit chip disposed above said substrate's upper surface, said integrated circuit chip having at least one interconnection pad on a top surface thereof, the top surface of said at least one integrated circuit chip being in a plane substantially parallel to said substrate's upper surface, said integrated circuit chip also having at least one side surface; said component being positioned within said substrate hole such that said component's upper surface is substantially parallel to said substrate's upper surface; an encapsulant surrounding said at least one integrated circuit chip including said top surface and said at least one side surface thereof, and contacting at least the upper surface of said circuit component, said encapsulant having an upper surface above the tops of the integrated circuit chip and the circuit component and having a plurality of via openings therein, said openings being aligned with at least some of said chip and component interconnection pads; and a pattern of interconnection conductors disposed above the upper surface of said encapsulant so as to extend between at least some of said openings and so as to provide electrical connection to at least some of said interconnection pads through said openings.

Claim 35

Multichip integrated circuit package comprising: a circuit component, said component having an upper surface with at least one interconnection pad thereon; a substrate having an upper surface and a lower surface, said substrate including a hole therein extending from said upper substrate surface to said lower substrate surface, said substrate hole being sized to accommodate said circuit component therein; at least one integrated circuit chip disposed above said substrate's upper surface, said integrated circuit chip having at least one interconnection pad on a top surface thereof, the top surface of said at least one integrated circuit chip being in a plane substantially parallel to said substrate's upper surface, said integrated circuit chip also having at least one side surface; said component being positioned within said substrate hole such that said component's upper surface is substantially parallel to said substrate's upper surface; an encapsulant surrounding said at least one integrated circuit chip including said top surface and said at least one side surface thereof, and contacting at least the upper surface of said circuit component, said encapsulant having an upper surface above the tops of the integrated circuit chip and the circuit component and having a plurality of via openings therein, said openings being aligned with at least some of said chip and component interconnection pads; and a pattern of interconnection conductors disposed above the upper surface of said encapsulant so as to extend between at least some of said openings and so as to provide electrical connection to at least some of said interconnection pads through said openings.

Claim 36

The integrated circuit package of claim 33, wherein a plurality of integrated circuit chips are disposed on said substrate's upper surface, each of said circuit chips having at least one interconnection pad on the top surface thereof.

Claim 37

The integrated circuit package of claim 34, wherein said substrate upper surface is flat.

Claim 38

The integrated circuit package of claim 34, wherein the top surfaces of said integrated circuit chips and the upper surface of said circuit component are substantially coplanar, said plane being parallel to the upper surface of said substrate.

Claim 39

The integrated circuit package of claim 36, further comprising means for securing said circuit component within said substrate hole such that the upper surface of said circuit component remains substantially in the same plane as the top surfaces of said integrated circuit chips.

Claim 40

The integrated circuit package of claim 34, wherein multiple substrate holes are provided, each of said through holes being sized to accommodate one of a plurality of circuit components.

Claim 41

The integrated circuit package of claim 34, wherein said substrate has a lower surface, and said package further comprises a well within said substrate disposed on said substrate's lower surface, said well being sized to accommodate a circuit component such that said component resides within said substrate well, said circuit component being electrically coupled to the upper surface of said substrate by metallized through holes extending through said substrate from said well to said upper substrate surface.

Claim 42

The hermetically packaged module of claim 39, wherein said multichip module has at least one side surface and wherein said sealing ring is attached to said at least one module side surface.

Claim 43

The hermetically packaged module of claim 40, wherein said lid's cover plate is ceramic.

Claim 44

The hermetically packaged module of claim 41, wherein said conductive means comprises a metallization extending through said cover plate openings.

Claim 45

The hermetically packaged module of claim 42, wherein said lid cover plate includes gold pads on each side thereof, each of said gold pads contacting one of said metallized cover plate openings.

Claim 46

A multichip integrated circuit package comprising: a substrate having an upper surface and a lower surface, said substrate having a well disposed on the lower surface thereof, said well being sized to accommodate a circuit component such that said component resides entirely within said substrate well; at least one integrated circuit chip disposed above said substrate's upper surface, said integrated circuit chip having at least one interconnection pad on a top surface thereof, the top surface of said at least one integrated circuit chip being in a plane substantially parallel to said substrate's upper surface, said integrated circuit chip also having at least one side surface; means for electrically coupling a circuit component disposed within said substrate well with the upper surface of said substrate; an encapsulant surrounding said at least one integrated circuit chip including said top surface and said at least one side surface thereof, and the upper surface of said substrate, said encapsulant having an upper surface above the top of said integrated circuit chip and having a plurality of via openings therein, said openings being aligned with at least some of said chip interconnection pads and said electrical means for coupling said circuit component disposed within said well to the upper surface of said substrate; and a pattern of interconnection conductors disposed above the upper surface of said encapsulant so as to extend between at least some of said openings and so as to provide electrical connection through said openings to at least some of said interconnection pads and said circuit component disposed within said well.

Claim 47

A multichip integrated circuit package comprising: a substrate having an upper surface and a lower surface, said substrate having a well disposed on the lower surface thereof, said well being sized to accommodate a circuit component such that said component resides entirely within said substrate well; at least one integrated circuit chip disposed above said substrate's upper surface, said integrated circuit chip having at least one interconnection pad on a top surface thereof, the top surface of said at least one integrated circuit chip being in a plane substantially parallel to said substrate's upper surface, said integrated circuit chip also having at least one side surface; means for electrically coupling a circuit component disposed within said substrate well with the upper surface of said substrate; an encapsulant surrounding said at least one integrated circuit chip including said top surface and said at least one side surface thereof, and the upper surface of said substrate, said encapsulant having an upper surface above the top of said integrated circuit chip and having a plurality of via openings therein, said openings being aligned with at least some of said chip interconnection pads and said electrical means for coupling said circuit component disposed within said well to the upper surface of said substrate; and a pattern of interconnection conductors disposed above the upper surface of said encapsulant so as to extend between at least some of said openings and so as to provide electrical connection through said openings to at least some of said interconnection pads and said circuit component disposed within said well.

Claim 48

The integrated circuit package of claim 44, wherein said electrical coupling means comprises at least two metallized through holes extending through said substrate from said well to said upper substrate surface.

Claim 49

The integrated circuit package of claim 44, wherein a plurality of integrated circuit chips are disposed on said substrate's upper surface, each of said circuit chips having at least one interconnection pad on the top surface thereof.

Claim 50

The integrated circuit package of claim 46, wherein said substrate's upper surface is flat.

Claim 51

A hermetically packaged multichip integrated circuit module comprising: a multichip module including: a substrate having an upper surface; a plurality of unpackaged integrated circuit chips disposed above said substrate's upper surface, said integrated circuit chips each being spaced apart from the other of said integrated circuit chips and each having at least one interconnection pad on a top surface thereof, the top surfaces of said integrated circuit chips being in a plane substantially parallel to said substrate's upper surface, said integrated circuit chips also each having at least one side surface; an encapsulant surrounding said integrated circuit chips including said top surfaces and said at least one side surfaces thereof and completely filling all space between adjacent integrated circuit chips disposed above said substrate's upper surface, said encapsulant having an upper surface above the tops of the integrated circuit chips and having a plurality of via openings therein, said openings being aligned with at least some of said interconnection pads; and a pattern of interconnection conductors disposed within at least some of said plurality of via openings and above the upper surface of said encapsulant so as to extend between said at least some of said plurality of via openings, and so as to provide direct electrical connection to at least some of said interconnection pads through said openings wherein a unitary module having multiple directly interconnected integrated circuit chip is produced, said pattern of interconnection conductors including at least one connection pad; a lid including an electrically insulating cover plate having a plurality of openings therethrough; conductive plugs hermetically disposed within said cover plate openings; means for electrically connecting at least one of said conductive plugs of said cover plate with at least one of said connection pads of said pattern of interconnection conductors; and means for hermetically sealing said lid about said single multichip module with said at least one conductive plug in electrical contact with said at least one connection pad of said pattern of interconnection conductors.

Claim 52

A hermetically packaged multichip integrated circuit module comprising: a multichip module including: a substrate having an upper surface; a plurality of unpackaged integrated circuit chips disposed above said substrate's upper surface, said integrated circuit chips each being spaced apart from the other of said integrated circuit chips and each having at least one interconnection pad on a top surface thereof, the top surfaces of said integrated circuit chips being in a plane substantially parallel to said substrate's upper surface, said integrated circuit chips also each having at least one side surface; an encapsulant surrounding said integrated circuit chips including said top surfaces and said at least one side surfaces thereof and completely filling all space between adjacent integrated circuit chips disposed above said substrate's upper surface, said encapsulant having an upper surface above the tops of the integrated circuit chips and having a plurality of via openings therein, said openings being aligned with at least some of said interconnection pads; and a pattern of interconnection conductors disposed within at least some of said plurality of via openings and above the upper surface of said encapsulant so as to extend between said at least some of said plurality of via openings, and so as to provide direct electrical connection to at least some of said interconnection pads through said openings wherein a unitary module having multiple directly interconnected integrated circuit chip is produced, said pattern of interconnection conductors including at least one connection pad; a lid including an electrically insulating cover plate having a plurality of openings therethrough; conductive plugs hermetically disposed within said cover plate openings; means for electrically connecting at least one of said conductive plugs of said cover plate with at least one of said connection pads of said pattern of interconnection conductors; and means for hermetically sealing said lid about said single multichip module with said at least one conductive plug in electrical contact with said at least one connection pad of said pattern of interconnection conductors.

Claim 53

The hermetically packaged module of claim 48, wherein said means for electrically connecting said at least one conductive plug with said at least one connection pad of said pattern of interconnection conductors comprises an array of button contacts disposed between said cover plate and the upper surface of said multichip module.

Claim 54

A hermetically packaged multichip integrated circuit module comprising: a multichip module including: a substrate having an upper surface; a plurality of unpackaged integrated circuit chips disposed above said substrate's upper surface, said integrated circuit chips each being spaced apart from the other of said integrated circuit chips and each having at least one interconnection pad on a top surface thereof, the top surfaces of said integrated circuit chips being in a plane substantially parallel to said substrate's upper surface, said integrated circuit chips also each having at least one side surface; an encapsulant surrounding said integrated circuit chips including said top surfaces and said at least one side surfaces thereof and completely filling all space between adjacent integrated circuit chips disposed above said substrate's upper surface, said encapsulant having an upper surface above the tops of the integrated circuit chips and having a plurality of via openings therein, said openings being aligned with at least some of said interconnection pads; and a pattern of interconnection conductors disposed within at least some of said plurality of via openings and above the upper surface of said encapsulant so as to extend between said at least some of said plurality of via openings and so as to provide direct electrical connection to at least some of said interconnection pads through said openings wherein a unitary module having multiple directly interconnected integrated circuit chips is produced, said pattern of interconnection conductors including at least one connection pad; a lid including an electrically insulating cover plate having a plurality of openings extending therethrough, said cover plate openings each being aligned with a connection pad on said pattern of interconnection conductors; conductive means hermetically disposed within each of said cover plate openings, at least one of said conductive means being in electrical contact with one of said connection pads of said pattern of interconnection conductors; and means for hermetically sealing said lid about said multichip module with said at least one conductive means in electrical contact with said connection pads of said pattern of interconnection conductors.

Claim 55

A hermetically packaged multichip integrated circuit module comprising: a multichip module including: a substrate having an upper surface; a plurality of unpackaged integrated circuit chips disposed above said substrate's upper surface, said integrated circuit chips each being spaced apart from the other of said integrated circuit chips and each having at least one interconnection pad on a top surface thereof, the top surfaces of said integrated circuit chips being in a plane substantially parallel to said substrate's upper surface, said integrated circuit chips also each having at least one side surface; an encapsulant surrounding said integrated circuit chips including said top surfaces and said at least one side surfaces thereof and completely filling all space between adjacent integrated circuit chips disposed above said substrate's upper surface, said encapsulant having an upper surface above the tops of the integrated circuit chips and having a plurality of via openings therein, said openings being aligned with at least some of said interconnection pads; and a pattern of interconnection conductors disposed within at least some of said plurality of via openings and above the upper surface of said encapsulant so as to extend between said at least some of said plurality of via openings and so as to provide direct electrical connection to at least some of said interconnection pads through said openings wherein a unitary module having multiple directly interconnected integrated circuit chips is produced, said pattern of interconnection conductors including at least one connection pad; a lid including an electrically insulating cover plate having a plurality of openings extending therethrough, said cover plate openings each being aligned with a connection pad on said pattern of interconnection conductors; conductive means hermetically disposed within each of said cover plate openings, at least one of said conductive means being in electrical contact with one of said connection pads of said pattern of interconnection conductors; and means for hermetically sealing said lid about said multichip module with said at least one conductive means in electrical contact with said connection pads of said pattern of interconnection conductors.

Claim 56

The hermetically packaged module of claim 50, further including a sealing ring disposed about said module and sealed to said cover plate.

Claim 57

The hermetically packaged module of claim 51, wherein a lower surface of said module's substrate is secured to said sealing ring.

Claim 58

The hermetically packaged module of claim 51, wherein said module has at least one side surface and wherein said sealing ring is sealed to said at least one module side surface.

Claim 59

The hermetically packaged module of claim 50, wherein said module's substrate forms a portion of said hermetic packaging.