Digital potentiometer with stackable configuration

Claim 2

An integrated circuit, comprising: first and second passive resistor strings; control circuitry, connected to receive a digital signal which includes first and second bit fields and at least one higher-order command bit; switching devices, controlled by said control circuitry so that said first resistor string is connected to provide a first wiper output, corresponding to a potentiometer wiper position defined by said first bit field; and said second resistor string is connected to provide a second wiper output, corresponding to a potentiometer wiper position defined by said second bit field; and a multiplexer, connected to provide a wiper output which corresponds either to first or said second wiper output in accordance with the state of said higher-order command bit so that said first and second potentiometers can optionally be combined in series to form a single potentiometer.

Claim 3

The integrated circuit of claim 1, comprising only two of said passive resistor strings.

Claim 4

The integrated circuit of claim 1, wherein each of said resistor strings includes at least 256 tap points.

Claim 5

The integrated circuit of claim 1, wherein each of said resistor strings comprises a polysilicon resistor.

Claim 6

The integrated circuit of claim 1, wherein said control circuitry comprises a serial port interface which is connected to receive said digital signal.

Claim 7

The integrated circuit of claim 1, wherein said first bit field and said second bit field each include at least eight bits.

Claim 8

The integrated circuit of claim 1, wherein said control circuitry is connected to receive exactly one said higher-order command bit.

Claim 9

An integrated circuit, comprising: first, second, third, fourth, fifth, sixth, and seventh signal terminals; control circuitry, connected to receive a digital signal which indicates first and second desired resistance values, and which also indicates at least one higher-order command bit, and to control switching devices so that said first resistance value appears as a DC resistance between said first and second terminals, and said second and third terminals are also linked by a variable DC resistance of less than ten megohms; and said second resistance value appears as a DC resistance between said fourth and fifth terminals, and said fifth and sixth terminals are also linked by a variable DC resistance of less than ten megohms; and said seventh terminal is connected to either said second or said fifth terminal, in accordance with the value of said higher-order command bit; whereby, in a first mode of operation: said first, second, and third terminals can be connected to emulate a first potentiometer, with said second terminal providing the wiper terminal thereof, and said fourth, fifth, and sixth terminals can be connected to emulate a second potentiometer, with said fifth terminal providing the wiper terminal thereof; and whereby, in a second mode of operation, if said third and fourth terminals are shorted together: said first, seventh, and sixth terminals can be connected to emulate a single potentiometer, with said seventh terminal providing the wiper terminal thereof, said potentiometer having a resulting effective setting which is defined by all bits of said first resistance value, by multiple bits of said second resistance values, and by said higher-order command bit, so that said single potentiometer has a higher effective resolution that said first potentiometer or said second potentiometer.

Claim 10

An integrated circuit, comprising: first, second, third, fourth, fifth, sixth, and seventh signal terminals; control circuitry, connected to receive a digital signal which indicates first and second desired resistance values, and which also indicates at least one higher-order command bit, and to control switching devices so that said first resistance value appears as a DC resistance between said first and second terminals, and said second and third terminals are also linked by a variable DC resistance of less than ten megohms; and said second resistance value appears as a DC resistance between said fourth and fifth terminals, and said fifth and sixth terminals are also linked by a variable DC resistance of less than ten megohms; and said seventh terminal is connected to either said second or said fifth terminal, in accordance with the value of said higher-order command bit; whereby, in a first mode of operation: said first, second, and third terminals can be connected to emulate a first potentiometer, with said second terminal providing the wiper terminal thereof, and said fourth, fifth, and sixth terminals can be connected to emulate a second potentiometer, with said fifth terminal providing the wiper terminal thereof; and whereby, in a second mode of operation, if said third and fourth terminals are shorted together: said first, seventh, and sixth terminals can be connected to emulate a single potentiometer, with said seventh terminal providing the wiper terminal thereof, said potentiometer having a resulting effective setting which is defined by all bits of said first resistance value, by multiple bits of said second resistance values, and by said higher-order command bit, so that said single potentiometer has a higher effective resolution that said first potentiometer or said second potentiometer.

Claim 11

The integrated circuit of claim 8, wherein said control circuitry comprises a serial port interface which is connected to receive said digital signal.

Claim 12

The integrated circuit of claim 2, wherein said control circuitry is connected to receive exactly one said higher-order command bit.