US4862136A
Expired / Lapsed
US
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Programmable resistance network
Assignee: Individual
•
Filing: 1983-04-13
•
Granted: 1989-08-29
•
Expires: 2003-04-13
Abstract
Abstract A programmable resistor network and a method for forming and programming same. The network includes a plurality of independent programmable resistor arrays in a standard DIP semiconductor package. Each resistor array includes a plurality of parallel connected resistor elements capable of being selectively deleted from the array of applying a programming flow of electricity across a first and second DIP pin. The flow of electricity is of a value sufficient to progressively fuse successive array resistors. The total array resistance value progressively increases as array resistors are selectively deleted. Typically an increasing flow of electricity is applied across the array terminals until the desired array resistance value is obtained. The arrays may be manufactured in such a way that the incremental value between successive resistive elements causes the total array resistance value to increase in any desired manner, e.g. geometrically, arithmetically, and logarithmically.
Inventors
- 👤 John M. Birkner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:33
CPC Classifications
H; H01; H01C; H01C10/00; H01C10/16
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
65 words
A programmable resistance network, comprising: an array of resistors capable of being selectively deleted by applying a programming flow of electricity across first and a second array terminals, said flow of electricity having a value sufficient to progressively fuse successive array resistors, each successive array resistor having the property of being fusible at a progressively greater flow of electricity than that of preceding array resistors.
Claim 2
Dependent Claim
65 words
A programmable resistance network, comprising: an array of resistors capable of being selectively deleted by applying a programming flow of electricity across first and a second array terminals, said flow of electricity having a value sufficient to progressively fuse successive array resistors, each successive array resistor having the property of being fusible at a progressively greater flow of electricity than that of preceding array resistors.
Claim 3
Dependent Claim
25 words
The resistance network of claim 1, further comprising each successive array resistor having a progressively higher resistance value than that of a preceding array resistors.
Claim 4
Dependent Claim
16 words
The programmable resistance network of claim 1, further comprising a plurality of independent programmable resistor arrays.
Claim 5
Dependent Claim
57 words
A programmable resistance network, comprising: an array of resistors capable of being selectively deleted by applying a programming flow of electricity across a first and a second array terminal, said flow of electricity having a value sufficient to progressively fuse successive array resistors, the total array resistance being progressively increased as said array resistors are selectively deleted.
Claim 6
Dependent Claim
57 words
A programmable resistance network, comprising: an array of resistors capable of being selectively deleted by applying a programming flow of electricity across a first and a second array terminal, said flow of electricity having a value sufficient to progressively fuse successive array resistors, the total array resistance being progressively increased as said array resistors are selectively deleted.
Claim 7
Independent Claim
98 words
A method of manufacturing a programmable resistance network, comprising: depositing a film resistor layer comprising a compound of titanium and tungsten onto a substrate in accordance with a predetermined resistance pattern to form a resistor array, said array establishing an incremental resistance value for each resistor in the array; and depositing a conductive layer, according to a predetermined pattern, onto said substrate and over said resistor array to create a connector grid for forming terminals connected to said resistor array; wherein successively fusing said resistors by application of an increasing flow of electricity progressively increases total array value.
Claim 8
Independent Claim
98 words
A method of manufacturing a programmable resistance network, comprising: depositing a film resistor layer comprising a compound of titanium and tungsten onto a substrate in accordance with a predetermined resistance pattern to form a resistor array, said array establishing an incremental resistance value for each resistor in the array; and depositing a conductive layer, according to a predetermined pattern, onto said substrate and over said resistor array to create a connector grid for forming terminals connected to said resistor array; wherein successively fusing said resistors by application of an increasing flow of electricity progressively increases total array value.
Claim 9
Dependent Claim
80 words
A programmable resistance network, comprising: a first elongate resistor array terminal; a second elongate resistor array terminal askew from said first terminal; and a plurality of parallel resistors connected as an array between said first and second terminals, each successive resistor having a progressively higher resistance value than that of preceding resistors, said resistors having the property of being selectively deletable by applying an increasing flow of electricity across said first and second terminals to progressively fuse successive array resistors.
Claim 10
Dependent Claim
80 words
A programmable resistance network, comprising: a first elongate resistor array terminal; a second elongate resistor array terminal askew from said first terminal; and a plurality of parallel resistors connected as an array between said first and second terminals, each successive resistor having a progressively higher resistance value than that of preceding resistors, said resistors having the property of being selectively deletable by applying an increasing flow of electricity across said first and second terminals to progressively fuse successive array resistors.
Claim 11
Dependent Claim
24 words
The resistance network of claim 6, further comprising each successive array resistor having a progressively higher resistance value than that of preceding array resistors.
Claim 12
Dependent Claim
21 words
The resistance network of claim 6, wherein total array resistance value is progressively increased as said array resistors are selectively deleted.
Claim 13
Dependent Claim
18 words
The resistance network of claim 8, wherein said total array resistance value has the property of increasing linearly.
Claim 14
Dependent Claim
18 words
The resistance network of claim 8, wherein said total array resistance value has the property of increasing logarithmically.
Claim 15
Dependent Claim
23 words
The resistance network of claim 8, wherein said total array resistance value has the property of increasing according to a simple interest rate.
Claim 16
Dependent Claim
18 words
The resistance network of claim 8, wherein said total array resistance value has the property of increasing geometrically.
Claim 17
Dependent Claim
18 words
The resistance network of claim 8, wherein said total array resistance value has the property of increasing exponentially.
Claim 18
Dependent Claim
18 words
The resistance network of claim 8, wherein said total array resistance value has the property of increasing arithmetically.
Claim 19
Dependent Claim
19 words
The programmable resistance network of claim 8, wherein said total array resistance value has the property of increasing hyperbolically.
Claim 20
Dependent Claim
15 words
The resistance network of claim 6, further comprising a plurality of independent programmable resistor arrays.
Claim 21
Dependent Claim
93 words
An integrated circuit programmable resistance network, comprising: a first elongate resistor terminal; a plurality of elongate parallel film resistors of progressively increasing length, said resistors having a first end connected to, and substantially perpendicular to said first terminal, each resistor having a resistance value that is a function of its length; and a second elongate resistor terminal connected to said resistors at a second resistor end, said resistors having the property of being selectively deletable by applying an increasing flow of electricity across said first and second terminals to progressively fuse successive resistors.
Claim 22
Dependent Claim
93 words
An integrated circuit programmable resistance network, comprising: a first elongate resistor terminal; a plurality of elongate parallel film resistors of progressively increasing length, said resistors having a first end connected to, and substantially perpendicular to said first terminal, each resistor having a resistance value that is a function of its length; and a second elongate resistor terminal connected to said resistors at a second resistor end, said resistors having the property of being selectively deletable by applying an increasing flow of electricity across said first and second terminals to progressively fuse successive resistors.
Claim 23
Dependent Claim
17 words
The resistance network of claim 17, wherein said increasing flow of electricity is an increasing electrical voltage.
Claim 24
Dependent Claim
17 words
The resistance network of claim 17, wherein said increasing flow of electricity is an increasing electric current.
Claim 25
Dependent Claim
15 words
The resistance network of claim 17, further comprising a plurality of independent programmable resistor arrays.
Claim 26
Dependent Claim
174 words
In an integrated circuit including a semiconductor substrate and having a dual in-line pin (DIP) package, a monolithic programmable resistor network, including a plurality of independent resistor arrays, each resistor array comprising: a film resistor layer deposited onto said substrate, said resistor layer arranged to form a pattern of parallel resistive layer arranged to form a pattern of parallel resistive elements, each successive resistance element being of greater length and resistance value than that preceding it; and a conductive layer deposited onto said resistive layer, said conductive layer arranged to form a first resistor array terminal at one end of said parallel resistive elements and to form a second resistor array terminal at another end of said parallel resistive elements, said first and second resistor array terminals being connected to a first and second DIP package pin, respectively, wherein a selected flow of a programmable voltage provided across said first and second DIP package pins progressively fuses successive resistive elements in said resistor array and provides a progressively increasing total resistor array resistance value.
Claim 27
Dependent Claim
174 words
In an integrated circuit including a semiconductor substrate and having a dual in-line pin (DIP) package, a monolithic programmable resistor network, including a plurality of independent resistor arrays, each resistor array comprising: a film resistor layer deposited onto said substrate, said resistor layer arranged to form a pattern of parallel resistive layer arranged to form a pattern of parallel resistive elements, each successive resistance element being of greater length and resistance value than that preceding it; and a conductive layer deposited onto said resistive layer, said conductive layer arranged to form a first resistor array terminal at one end of said parallel resistive elements and to form a second resistor array terminal at another end of said parallel resistive elements, said first and second resistor array terminals being connected to a first and second DIP package pin, respectively, wherein a selected flow of a programmable voltage provided across said first and second DIP package pins progressively fuses successive resistive elements in said resistor array and provides a progressively increasing total resistor array resistance value.
Claim 28
Dependent Claim
46 words
The resistor array of claim 21, further comprising said second resistor array terminal having a selectable contour for varying incremental length of successive resistive elements and for progressively increasing total resistor array resistance value according to a selected incremental progression as successive resistive elements are fused.
Claim 29
Independent Claim
44 words
A method of selecting a desired resistance value, comprising progressively fusing successive resistors in a resistor array by applying a progressively greater flow of electricity across array terminals including the step of progressively increasing total array resistance value by selectively deleting said array resistors.
Claim 30
Independent Claim
44 words
A method of selecting a desired resistance value, comprising progressively fusing successive resistors in a resistor array by applying a progressively greater flow of electricity across array terminals including the step of progressively increasing total array resistance value by selectively deleting said array resistors.
Claim 31
Independent Claim
91 words
A method of manufacturing a programmable resistance network, comprising: depositing a film resistor layer onto a substrate in accordance with a predetermined resistance pattern to form a resistor array, said array establishing an incremental resistance value for each resistor in the array; and depositing an aluminum layer, according to a predetermined pattern, onto said substrate and over said resistor array to create a connector grid for forming terminals connected to said resistor array; wherein successively fusing said resistors by application of an increasing flow of electricity progressively increases total array value.
Claim 32
Independent Claim
91 words
A method of manufacturing a programmable resistance network, comprising: depositing a film resistor layer onto a substrate in accordance with a predetermined resistance pattern to form a resistor array, said array establishing an incremental resistance value for each resistor in the array; and depositing an aluminum layer, according to a predetermined pattern, onto said substrate and over said resistor array to create a connector grid for forming terminals connected to said resistor array; wherein successively fusing said resistors by application of an increasing flow of electricity progressively increases total array value.
Claim 33
Independent Claim
137 words
A method of manufacturing a programmable resistance network comprising: depositing a film resistor layer onto a substrate in accordance with a predetermined resistance pattern to form a resistor array, said array establishing an incremental resistance value for each resistor in the array; and depositing a conductive layer, according to a predetermined pattern, onto said substrate and over said resistor array to create a connector grid for forming terminals connected to said resistor array; wherein successively fusing said resistor by application of an increasing flow of electricity progressively increases total array value, said step of depositing including the step of varying the incremental length of successive resistive elements by forming said conductive layer with a selected conductor contour to progressively increase total resistor array resistance value according to a selected incremental progression as successive resistive elements are fused.
Claim 34
Independent Claim
137 words
A method of manufacturing a programmable resistance network comprising: depositing a film resistor layer onto a substrate in accordance with a predetermined resistance pattern to form a resistor array, said array establishing an incremental resistance value for each resistor in the array; and depositing a conductive layer, according to a predetermined pattern, onto said substrate and over said resistor array to create a connector grid for forming terminals connected to said resistor array; wherein successively fusing said resistor by application of an increasing flow of electricity progressively increases total array value, said step of depositing including the step of varying the incremental length of successive resistive elements by forming said conductive layer with a selected conductor contour to progressively increase total resistor array resistance value according to a selected incremental progression as successive resistive elements are fused.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-28 | 1993-02-27 | 1993-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-28 | 1997-02-27 | 1997-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-28 | 2001-02-27 | 2001-08-29 | $7700.00 | Window Closed / Lapsed |