US4849903A
Expired / Lapsed
US
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Digitally controlled system for effecting and presenting a selected electrical resistance
Assignee: National Aeronautics and Space Administration
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Filing: 1987-07-15
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Granted: 1989-07-18
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Expires: 2007-07-15
Abstract
Abstract A digitally controlled resistance generator (10) in which resistors (16-38) having values selected according to an expression 2N-1(R), where N is equal to the number of terms in the expression, and R is equal to the lowest value of resistance, are electrically inserted into a resistive circuit in accordance with a parallel binary signal provided by an analog-to-digital converter (46) or a programmable computer (75). This binary signal is coupled via optical isolators (50-72) which, when activated by a logical "1," provides a negative potential to some or all of the gate inputs (96) of the normally "on" field effect transistors (98-120) which, when "on," shorts out the associated resistor. This applied negative potential turns the field effect transistors "off" and electrically inserts the resistor coupled between the source terminal (124) and the drain terminal (122) of that field effect transistor into the resistive circuit between the terminals (12, 14).
Inventors
- 👤 James C. Fletcher
- 👤 Walter L. Ross
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:35
CPC Classifications
G; G01; G01R; G01R1/00; G01R1/20; G01R1/203
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
204 words
A digitally controlled system for effecting and presenting a selected electrical resistance, said system comprising: digital means for providing a plurality of separate binary outputs, each representative of a separate numerical value of a binary count, and each representative of a discrete selected value of resistance; a plurality of switching means, each having a control input coupled to a corresponding one of said plurality of binary outputs, and each of said switching means further including a set of first and second switched terminals, said terminals being electrically switched between a shorted or opened condition responsive to a discrete one of said binary outputs, said sets of switched terminals being serially connected; and a plurality of serially coupled resistors having resistive values selected according to an expression 2 N-1 (R), where N is the number of terms in said expression, and R is a lowest value of resistance, with discrete ones of said plurality of resistors being connected across discrete said sets of said switched terminals, and said plurality of resistors ordered in their connections to said plurality of sets of terminals such that, when selected resistors are electrically summed, a linear sequence of numerical values of resistance is generated responsive to said digital means.
Claim 2
Dependent Claim
204 words
A digitally controlled system for effecting and presenting a selected electrical resistance, said system comprising: digital means for providing a plurality of separate binary outputs, each representative of a separate numerical value of a binary count, and each representative of a discrete selected value of resistance; a plurality of switching means, each having a control input coupled to a corresponding one of said plurality of binary outputs, and each of said switching means further including a set of first and second switched terminals, said terminals being electrically switched between a shorted or opened condition responsive to a discrete one of said binary outputs, said sets of switched terminals being serially connected; and a plurality of serially coupled resistors having resistive values selected according to an expression 2 N-1 (R), where N is the number of terms in said expression, and R is a lowest value of resistance, with discrete ones of said plurality of resistors being connected across discrete said sets of said switched terminals, and said plurality of resistors ordered in their connections to said plurality of sets of terminals such that, when selected resistors are electrically summed, a linear sequence of numerical values of resistance is generated responsive to said digital means.
Claim 3
Dependent Claim
55 words
A system as set forth in claim 1 wherein said plurality of resistors are mounted on a carrier having electrical contact pins, and said plurality of resistors is electrically coupled to said pins, said pins being pluggable into a matching receptacle connected in circuit with said switch means, whereby a range of resistance is changed.
Claim 4
Dependent Claim
58 words
A system as set forth in claim 2 comprising: a decimal decoder having a plurality of inputs and an output, said plurality of inputs coupled to said plurality of binary outputs of said analog-to-digital conversion means; and a digital display having an input coupled to said output of said decimal decoder, whereby a value of resistance is displayed.
Claim 5
Dependent Claim
44 words
A system as set forth in claim 1 wherein said digital means comprises a programmable digital computer including buffer storage means having a plurality of ordered binary storage locations coupled to said computer for providing temporary storage for said plurality of separate binary outputs.
Claim 6
Dependent Claim
45 words
A system as set forth in claim 4 wherein said digital means comprises: variable voltage means, including a potentiometer coupled to a voltage source, for providing a variable voltage; and analog-to-digital conversion means responsive to said variable voltage for providing said plurality of binary outputs.
Claim 7
Dependent Claim
134 words
A system as set forth in claim 1 wherein each of said plurality of switching means comprises: optical couplers having said control input and third and fourth terminals comprising emitter and collector terminals, respectively, of a light responsive transistor, said emitter and collector terminals being switched responsive to a discrete one of said binary outputs applied to said control input; and a field effect transistor having a gate input coupled to said collector terminal, and wherein said first and second switched terminals comprise source and drain terminals of said field effect transistor, whereby a discrete one of said binary outputs is electrically isolated from one of said plurality of resistors coupled between said source and said drain terminals, and said last-named output is optically coupled to said gate input of said field effect transistor.
Claim 8
Dependent Claim
68 words
A system as set forth in claim 6 comprising positive bias voltage means coupled between each said collector terminal of each said light responsive transistor and each said gate input of said plurality of field effect transistors for providing a positive bias with respect to ground to each said gate input of each said field effect transistor, whereby said plurality of field effect transistors are biased normally "on."
Claim 9
Dependent Claim
89 words
A system as set forth in claim 6 comprising negative bias voltage means coupled to said emitter of each said light responsive transistor for applying a negative bias to selected gate inputs of selected said field effect transistors, whereby said selected field effect transistors are biased "off" responsive to discrete ones of said binary outputs applied to said selected control inputs, thereby including a selected resistor connected between said source and drain terminals of said selected field effect transistors in circuit with said selected resistors which are electrically summed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-17 | 1993-01-16 | 1993-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-17 | 1997-01-16 | 1997-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-17 | 2001-01-16 | 2001-07-18 | $7700.00 | Window Closed / Lapsed |