US5065132A — Programmable resistor and an array of the same

Claim 1

Independent Claim 67 words

A programmable resistor, comprising: a substrate formed of a layer of semiconductor of a first type; a current path region of a second type formed in said substrate wherein an interface having interfacial traps is formed between said current path and said substrate; a backgate formed adjacent said current path; and circuitry coupled to said backgate for varying the number of carriers residing in said interfacial traps.

Claim 2

Dependent Claim 67 words

A programmable resistor, comprising: a substrate formed of a layer of semiconductor of a first type; a current path region of a second type formed in said substrate wherein an interface having interfacial traps is formed between said current path and said substrate; a backgate formed adjacent said current path; and circuitry coupled to said backgate for varying the number of carriers residing in said interfacial traps.

Claim 3

Dependent Claim 19 words

The programmable resistor of claim 1, wherein said current path comprises a channel area of a field effect transistor.

Claim 4

Dependent Claim 18 words

The programmable resistor of claim 2, wherein said field effect transistor comprises a metal semiconductor field effect transistor.

Claim 5

Dependent Claim 19 words

The programmable resistor of claim 2, wherein said field effect transistor comprises a metal oxide semiconductor field effect transistor.

Claim 6

Dependent Claim 85 words

A programmable resistor, comprising: a field effect transistor including a channel area formed in a layer of semiconductor so as to create a plurality of interfacial traps along an interface between the channel and the layer of semiconductor; a backgate spaced from said channel area operable to vary the resistance of the channel area responsive to a voltage applied thereto; a first switch selectively coupling said backgate to a first voltage source; and a second switch selectively coupling said backgate to a second voltage source.

Claim 7

Dependent Claim 85 words

A programmable resistor, comprising: a field effect transistor including a channel area formed in a layer of semiconductor so as to create a plurality of interfacial traps along an interface between the channel and the layer of semiconductor; a backgate spaced from said channel area operable to vary the resistance of the channel area responsive to a voltage applied thereto; a first switch selectively coupling said backgate to a first voltage source; and a second switch selectively coupling said backgate to a second voltage source.

Claim 8

Dependent Claim 27 words

The programmable resistor of claim 5, wherein said layer of semiconductor is of a first type and said channel area is of a second type formed therein.

Claim 9

Dependent Claim 28 words

The programmable resistor of claim 5, wherein said first switch couples said backgate to a positive voltage and said second switch couples said backgate to a negative voltage.

Claim 10

Dependent Claim 28 words

The programmable resistor of claim 5, wherein said channel area is formed of N type gallium arsenide and said layer of semiconductor is formed of semi-insulating gallium arsenide.

Claim 11

Dependent Claim 27 words

The programmable resistor of claim 5, wherein said channel area is formed of N type silicon and said layer of semiconductor is formed of P type silicon.

Claim 12

Dependent Claim 26 words

The programmable resistor of claim 5, wherein said channel is formed of P type silicon and said layer of semiconductor is formed of N type silicon.

Claim 13

Dependent Claim 28 words

The programmable resistor of claim 5, wherein said channel area is formed of P type gallium arsenide and said layer of semiconductor is formed of semi-insulating gallium arsenide.

Claim 14

Dependent Claim 138 words

A programmable resistor, comprising: a field effect transistor formed in a semiconductor substrate of a first type conductivity comprising: a source region of a second conductivity type formed in said substrate; a drain region of said second conductivity type formed adjacent said substrate; a channel area of said second conductivity type formed adjacent said substrate, such that an interface having interfacial traps with said substrate is formed therebetween; and a gate formed adjacent to said channel area; a backgate spaced from said channel area and formed adjacent said substrate to be of said second conductivity type such that the resistance of the channel area can be varied responsive to a voltage applied to the backgate; a first switch selectively connecting said backgate to a first voltage; and a second switch selectively connecting said backgate to a second voltage.

Claim 15

Dependent Claim 138 words

A programmable resistor, comprising: a field effect transistor formed in a semiconductor substrate of a first type conductivity comprising: a source region of a second conductivity type formed in said substrate; a drain region of said second conductivity type formed adjacent said substrate; a channel area of said second conductivity type formed adjacent said substrate, such that an interface having interfacial traps with said substrate is formed therebetween; and a gate formed adjacent to said channel area; a backgate spaced from said channel area and formed adjacent said substrate to be of said second conductivity type such that the resistance of the channel area can be varied responsive to a voltage applied to the backgate; a first switch selectively connecting said backgate to a first voltage; and a second switch selectively connecting said backgate to a second voltage.

Claim 16

Dependent Claim 14 words

The programmable resistor of claim 12, wherein said gate comprises a Schottky barrier gate.

Claim 17

Dependent Claim 20 words

The programmable resistor of claim 12, wherein said gate is separated from said channel area by a layer of insulator.

Claim 18

Dependent Claim 40 words

The programmable resistor of claim 12, wherein said source and drain regions and said backgate comprise heavily doped diffused regions of said second conductivity type and said channel area comprises a lightly doped diffused region of said second conductivity type.

Claim 19

Dependent Claim 24 words

The programmable resistor of claim 15, wherein said source and drain regions and said backgate comprise n+regions and said channel area comprises an n-area.

Claim 20

Dependent Claim 30 words

The programmable resistor of claim 12 and further comprising an isolation region formed in said layer of semiconductor and laterally enclosing at least said field effect transistor and said backgate.

Claim 21

Dependent Claim 16 words

The programmable resistor of claim 17 wherein said isolation region comprises an electrically biased conductive region.

Claim 22

Dependent Claim 17 words

The programmable resistor of claim 17 and further comprising a thick insulator layer overlying said isolation region.

Claim 23

Dependent Claim 17 words

The programmable resistor of claim 19 wherein said thick insulator layer comprises a layer of thick oxide.

Claim 24

Dependent Claim 99 words

A neural network array comprising: a plurality of input lines; a plurality of output lines; a plurality of programmable resistors coupling each of said input lines with each of said output lines, said programmable resistors comprising: a substrate formed of a layer of semiconductor of a first type; a current path region of a second type formed in said substrate wherein an interface having interfacial traps is formed between said current path and said substrate; a backgate formed adjacent said current path; and circuitry coupled to said backgate for varying the number of carriers residing in said interfacial traps.

Claim 25

Dependent Claim 99 words

A neural network array comprising: a plurality of input lines; a plurality of output lines; a plurality of programmable resistors coupling each of said input lines with each of said output lines, said programmable resistors comprising: a substrate formed of a layer of semiconductor of a first type; a current path region of a second type formed in said substrate wherein an interface having interfacial traps is formed between said current path and said substrate; a backgate formed adjacent said current path; and circuitry coupled to said backgate for varying the number of carriers residing in said interfacial traps.

Claim 26

Independent Claim 67 words

A method for providing a variable resistance element in a semiconductor substrate, comprising the steps of: generating a current flow through a doped region of a first conductivity type having an interface with a substrate of a second conductivity type; increasing the resistance of the doped region by filling the traps with electrons; and decreasing the resistance of the current path by removing electrons from the traps.

Claim 27

Independent Claim 67 words

A method for providing a variable resistance element in a semiconductor substrate, comprising the steps of: generating a current flow through a doped region of a first conductivity type having an interface with a substrate of a second conductivity type; increasing the resistance of the doped region by filling the traps with electrons; and decreasing the resistance of the current path by removing electrons from the traps.

Claim 28

Dependent Claim 48 words

The method of claim 21, wherein said step of increasing the resistance of the current path comprises the step of applying a voltage to a backgate formed in the substrate spaced from the doped region such that the barrier height between the traps and the backgate is reduced.

Claim 29

Dependent Claim 43 words

The method of claim 21, wherein said step of decreasing the resistance of the current path comprises the step of applying a voltage to the backgate such that the barrier width between the traps and the backgate is reduced wherein electrons are removed.

Claim 30

Dependent Claim 52 words

The method of claim 21, wherein said step of generating a current flow comprises the steps of creating a voltage difference between the source and the drain of a field effect transistor and applying a voltage to the gate of the field effect transistor to control the conductivity of the channel area.

Claim 31

Independent Claim 91 words

A method for forming a programmable resistor at a face of a layer of semiconductor of a first conductivity type, comprising the steps of: forming a horizontal portion of a backgate of a second conductivity type by an implant into the face of the layer of semiconductor; forming a vertical portion of the backgate continuous with the horizontal portion by an implant into the face of the layer of semiconductor; and forming source and drain regions of the second conductivity type spaced by a channel area of the second conductivity type.

Claim 32

Independent Claim 91 words

A method for forming a programmable resistor at a face of a layer of semiconductor of a first conductivity type, comprising the steps of: forming a horizontal portion of a backgate of a second conductivity type by an implant into the face of the layer of semiconductor; forming a vertical portion of the backgate continuous with the horizontal portion by an implant into the face of the layer of semiconductor; and forming source and drain regions of the second conductivity type spaced by a channel area of the second conductivity type.

Claim 33

Dependent Claim 26 words

The method of claim 26 and further comprising the step of implanting an isolation region laterally enclosing the source drain, the backgate and the channel area.

Claim 34

Dependent Claim 21 words

The method of claim 26 and further comprising the step of forming a layer of thick insulator overlying the isolation region.

Claim 35

Independent Claim 125 words

A method for forming a programmable resistor at a face of a layer of semiconductor of a first conductivity type, comprising the steps of: forming a horizontal portion of a backgate of a second conductivity type by epitaxial growth; forming a second layer of semiconductor of the first conductivity type adjacent the horizontal portion of the backgate; forming a vertical portion of the backgate continuous with the horizontal portion by at least one implant into the face of the second layer of semiconductor; and forming source and drain regions of the second conductivity type spaced by a channel area of the second conductivity type, the source, drain and channel area formed by at least one implant into the face of the second layer of semiconductor.

Claim 36

Independent Claim 125 words

A method for forming a programmable resistor at a face of a layer of semiconductor of a first conductivity type, comprising the steps of: forming a horizontal portion of a backgate of a second conductivity type by epitaxial growth; forming a second layer of semiconductor of the first conductivity type adjacent the horizontal portion of the backgate; forming a vertical portion of the backgate continuous with the horizontal portion by at least one implant into the face of the second layer of semiconductor; and forming source and drain regions of the second conductivity type spaced by a channel area of the second conductivity type, the source, drain and channel area formed by at least one implant into the face of the second layer of semiconductor.

Claim 37

Independent Claim 146 words

A method for forming a programmable resistor at a face of a layer of semiconductor of a first conductivity type, comprising the steps of: forming a horizontal portion of a backgate of a second conductivity type by epitaxial growth; forming a second layer of semiconductor of the first conductivity type adjacent the horizontal portion of the backgate; forming a vertical portion of the backgate continuous with the horizontal portion of the backgate by implantation and a channel area of the second conductivity type by epitaxial growth of semiconductor of the second conductivity type; forming a top layer of semiconductor of the second conductivity type vertically adjacent the channel area by epitaxial growth; and defining the boundaries of a source region, a drain region and a vertical extension of the backgate, each vertically spaced from the channel area, by an etch of the top layer of semiconductor.

Claim 38

Independent Claim 146 words

A method for forming a programmable resistor at a face of a layer of semiconductor of a first conductivity type, comprising the steps of: forming a horizontal portion of a backgate of a second conductivity type by epitaxial growth; forming a second layer of semiconductor of the first conductivity type adjacent the horizontal portion of the backgate; forming a vertical portion of the backgate continuous with the horizontal portion of the backgate by implantation and a channel area of the second conductivity type by epitaxial growth of semiconductor of the second conductivity type; forming a top layer of semiconductor of the second conductivity type vertically adjacent the channel area by epitaxial growth; and defining the boundaries of a source region, a drain region and a vertical extension of the backgate, each vertically spaced from the channel area, by an etch of the top layer of semiconductor.

Claim 39

Dependent Claim 76 words

The method of claim 30 and further comprising the steps of: performing at least one compensating implant into the face of the top layer of semiconductor to form an isolation region of the first conductivity type, the isolation region enclosing the channel area and the horizontal portion of the backgate; and selectively creating isolation regions between the channel area, the vertical portion of the backgate by selectively damaging the lattice of the semiconductor therebetween by implantation.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1994-11-11	1995-05-13	1995-11-12	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1998-11-11	1999-05-13	1999-11-12	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2002-11-11	2003-05-13	2003-11-12	$7700.00	Window Closed / Lapsed

Programmable resistor and an array of the same

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag