Data output buffer circuit with precharged bootstrap circuit

Claim 1

A data output buffer circuit comprising: a pair of data lines respectively applied with a noninverted data signal and an inverted data signal; output gate means for gating said noninverted and inverted data signals in response to an output enable signal; a transistor pair comprising a pull-up and a pull-down NMOS transistor connected in series between a first supply voltage and a ground voltage; a supply voltage converter circuit, responsive to said first supply voltage, for generating a constant second supply voltage so long as said first supply voltage is above a predetermined minimum level; and a bootstrap circuit, precharged by receiving said second supply voltage, for driving said pull-up NMOS transistor with a boosted voltage level when said non-inverted data signal is a logic "HIGH" state, said bootstrap circuit comprising: a first NMOS transistor for coupling the second supply voltage from said supply voltage converter circuit to a first terminal of a main capacitor; a secondary capacitor for fully turning on said first NMOS transistor during said logic "HIGH" state; a second NMOS transistor and a third NMOS transistor for coupling the second supply voltage to a first terminal of said secondary capacitor to precharge said secondary capacitor; overcurrent limit means for limiting overcurrent into said secondary capacitor; a first CMOS inverter, connected between the first terminal of said main capacitor and the ground voltage, for transferring the boosted voltage from the main capacitor to a gate electrode of said pull-up transistor during said logic "HIGH" state, and for transferring the ground voltage during a logic "LOW" state; and a second CMOS inverter, connected across said second supply voltage and the ground voltage, for transferring the second supply voltage to a second terminal of the main capacitor during said logic "HIGH" state, and for transferring the ground voltage thereto during said logic "LOW" state.