Semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit device comprising: an output node; a boost capacitor having a first terminal and a second terminal, wherein said second terminal is coupled to said output node; a voltage supply terminal to which a first voltage is supplied; precharge means coupled between said second terminal of said boost capacitor and said voltage supply terminal, and for precharging said boost capacitor at a predetermined precharge voltage; clock providing means for providing a clock signal; and voltage limitation means for providing a predetermined voltage less than said first voltage to said first terminal of said boost capacitor in response to said clock signal.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein said voltage limitation means comprises a MOSFET coupled to receive said clock signal at one electrode thereof and for providing said predetermined voltage from another electrode thereof, wherein a gate of said MOSFET is coupled to a voltage generating means.

Claim 4

A semiconductor integrated circuit device according to claim 2, further comprising control means coupled between a gate of said MOSFET and said voltage generating means.

Claim 5

A semiconductor integrated circuit device according to claim 3, wherein said voltage generating means comprises a first voltage generating means coupled between said control means and a third terminal to which said first voltage is supplied, and a second voltage generating means coupled between said control means and a fourth terminal to which a second voltage is supplied.

Claim 6

A semiconductor integrated circuit device according to claim 4, wherein said first voltage is higher than said second voltage.

Claim 7

A semiconductor integrated circuit device according to claim 3, wherein said control means comprises a first diode and a second diode wherein a first input terminal of said first diode is coupled to a second output terminal of said second diode and a first output terminal of said first diode is coupled to a second input terminal of said second diode, wherein said first input terminal of said first diode is coupled to said voltage limitation means and said first output terminal of said first diode is coupled to said gate of first MOSFET.

Claim 8

A semiconductor integrated circuit device according to claim 6, wherein said first diode and said second diode are constructed of a MOSFET, respectively.

Claim 9

A semiconductor integrated circuit device according to claim 2, wherein said voltage generating means comprises a first voltage generating means coupled between said gate of said MOSFET and a third terminal to which said first voltage is supplied, and a second voltage generating means coupled between said gate of said MOSFET and a fourth terminal to which a second voltage is supplied.

Claim 10

A semiconductor integrated circuit device according to claim 8, wherein said first voltage is higher than said second voltage.

Claim 11

A semiconductor integrated circuit device according to claim 1, wherein said precharge means includes at least one MOSFET.

Claim 12

A semiconductor integrated circuit device comprising: an output node for providing an output voltage greater than a predetermined reference voltage; a boost capacitor having a first terminal and a second terminal, wherein said second terminal is coupled to said output node; a third terminal to which said reference voltage is supplied; precharge means coupled between said second terminal of said boost capacitor and said third terminal, and for precharging said boost capacitor; signal providing means for providing a signal; and voltage limitation means coupled to said signal providing means and for limiting a voltage which is supplied to said first terminal in response to said signal to a predetermined voltage less than said reference voltage.

Claim 13

A semiconductor integrated circuit device comprising: an output node for providing an output voltage greater than a predetermined reference voltage; a boost capacitor having a first terminal and a second terminal, wherein said second terminal is coupled to said output node; a third terminal to which said reference voltage is supplied; precharge means coupled between said second terminal of said boost capacitor and said third terminal, and for precharging said boost capacitor; signal providing means for providing a signal; and voltage limitation means coupled to said signal providing means and for limiting a voltage which is supplied to said first terminal in response to said signal to a predetermined voltage less than said reference voltage.

Claim 14

A semiconductor integrated circuit device according to claim 11, wherein said voltage limitation means comprises a MOSFET coupled to receive said signal at one electrode and for providing said predetermined voltage from another electrode thereof, wherein a gate of said MOSFET is coupled to a voltage generating means.

Claim 15

A semiconductor integrated circuit device according to claim 12, further comprising control means coupled between a gate of said MOSFET and said voltage generating means.

Claim 16

A semiconductor integrated circuit device according to claim 13, wherein said voltage generating means comprises a first voltage generating means coupled between said control means and a third terminal to which said reference voltage is supplied, and a second voltage generating means coupled between said control means and a fourth terminal to which a second voltage is supplied.

Claim 17

A semiconductor integrated circuit device according to claim 14, wherein said reference voltage is greater than said second voltage.

Claim 18

A semiconductor integrated circuit device according to claim 13, wherein said control mean comprises a first diode and a second diode, wherein a first input terminal of said first diode is coupled to a second output terminal of said second diode and a first output terminal of said first diode is coupled to a second input terminal of said second diode, wherein said first input terminal of said first diode is coupled to said voltage limitation means and said first output terminal of said first diode is coupled to said gate of said MOSFET.

Claim 19

A semiconductor integrated circuit device according to claim 16, wherein said first diode and said second diode are constructed of a MOSFET, respectively.

Claim 20

A semiconductor integrated circuit device according to claim 12, wherein said voltage generating means comprises a first voltage generating means coupled between said gate of said MOSFET and a third terminal to which said reference voltage is supplied, and a second voltage generating means coupled between said gate of said MOSFET and a fourth terminal to which a second voltage is supplied.

Claim 21

A semiconductor integrated circuit device according to claim 18, wherein said reference voltage is greater than said second voltage.

Claim 22

A semiconductor integrated circuit device according to claim 11, wherein said precharge means is constructed of at least one MOSFET.

Claim 23

A semiconductor integrated circuit device comprising: a memory array which includes a plurality of word lines, a plurality of data lines, and a plurality of memory cells coupled in correspondence with said word lines and said data lines, respectively, first selection means for selecting a predetermined word line; second selection means for selecting a predetermined data line; and voltage generation means for supplying an output voltage to said first selection means, whereby a potential of the selected word line is set substantially at said output voltage, wherein said voltage generation means comprises: clock providing means for providing a clock signal, switching means for providing said output voltage in response to said clock signal, a boost capacitor having a second terminal and a first terminal coupled to said switching means, a terminal to which a first voltage is supplied, precharge means coupled between said first terminal of said boost capacitor and said terminal, and for precharging said boost capacitor at a predetermined precharge voltage, and voltage limitation means for providing a predetermined voltage less than said first voltage to said second terminal of said boost capacitor in response to said clock signal.

Claim 24

A semiconductor integrated circuit device comprising: a memory array which includes a plurality of word lines, a plurality of data lines, and a plurality of memory cells coupled in correspondence with said word lines and said data lines, respectively, first selection means for selecting a predetermined word line; second selection means for selecting a predetermined data line; and voltage generation means for supplying an output voltage to said first selection means, whereby a potential of the selected word line is set substantially at said output voltage, wherein said voltage generation means comprises: clock providing means for providing a clock signal, switching means for providing said output voltage in response to said clock signal, a boost capacitor having a second terminal and a first terminal coupled to said switching means, a terminal to which a first voltage is supplied, precharge means coupled between said first terminal of said boost capacitor and said terminal, and for precharging said boost capacitor at a predetermined precharge voltage, and voltage limitation means for providing a predetermined voltage less than said first voltage to said second terminal of said boost capacitor in response to said clock signal.

Claim 25

A semiconductor integrated circuit device according to claim 21, wherein said each memory cell includes a MOSFET and a capacitor element connected thereto.

Claim 26

A semiconductor integrated circuit device according to claim 21, wherein said first selection means comprises a first selector circuit and a second selector circuit, and MOSFETs which are coupled between said first selector circuit and said word lines and whose gates are supplied with an output of said second selector circuit, and wherein said output voltage of said voltage generation means is supplied to said first selector circuit.

Claim 27

A semiconductor integrated circuit device according to claim 21, wherein said voltage limitation means comprises a MOSFET coupled to receive said clock signal at one electrode and for providing said predetermined voltage from another electrode thereof, and wherein a gate of said MOSFET is coupled to a voltage generating means.

Claim 28

A semiconductor integrated circuit device according to claim 24, further comprising control means coupled between a gate of said MOSFET and said voltage generating means.

Claim 29

A semiconductor integrated circuit device according to claim 25, wherein said voltage generating means comprises a first voltage generating means coupled between said control means and a third terminal to which said first voltage is supplied, and a second voltage generating means coupled between said control means and a fourth terminal to which a second voltage is supplied.

Claim 30

A semiconductor integrated circuit device according to claim 26, wherein said first voltage is higher than said second voltage.

Claim 31

A semiconductor integrated circuit device according to claim 25, wherein said control means comprises a first diode and a second diode, wherein a first input terminal of said first diode is coupled to a second output terminal of said second diode and a first output terminal of said first diode is coupled to a second input terminal of said second diode, wherein said first input terminal of said first diode is coupled to said voltage limitation means and said first output terminal of said first diode is coupled to said gate of said MOSFET.

Claim 32

A semiconductor integrated circuit device according to claim 28, wherein said first diode and said second diode are constructed of MOSFET, respectively.

Claim 33

A semiconductor integrated circuit device according to claim 24, wherein said voltage generating means comprises a first voltage generating means coupled between said gate of said MOSFET and a third terminal to which said first voltage is supplied, and a second voltage generating means coupled between said gate of said MOSFET and a fourth terminal to which a second voltage is supplied.

Claim 34

A semiconductor integrated circuit device according to claim 30, wherein said first voltage is higher than said second voltage.

Claim 35

A semiconductor integrated circuit device according to claim 21, wherein said precharge means is constructed of at least one MOSFET.

Claim 36

A semiconductor integrated circuit device according to claim 21, wherein said switching means is constructed of a complementary MOSFET.

Claim 37

A semiconductor integrated circuit device comprising: a memory array which includes a plurality of word lines, a plurality of data lines, and a plurality of memory cells coupled in correspondence with said word lines and said data lines, respectively, first selection means for selecting a predetermined word line; second selection means for selecting a predetermined data line; and voltage generation mean for supplying an output voltage to said first selection means, whereby a potential of the selected word line is set substantially at said output voltage, wherein said voltage generation means comprises: signal providing means for providing a signal, switching means for providing said output voltage greater than a predetermined reference voltage in response to said signal, a boost capacitor having a first terminal and a second terminal, said second terminal being coupled to said switching means, a third terminal to which said reference voltage is supplied, precharge means coupled between said second terminal of said boost capacitor and said third terminal, and for precharging said boost capacitor, and voltage limitation means coupled to said signal providing means and for limiting a voltage which is supplied to said first terminal in response to said signal to a predetermined voltage less than said reference voltage.

Claim 38

A semiconductor integrated circuit device comprising: a memory array which includes a plurality of word lines, a plurality of data lines, and a plurality of memory cells coupled in correspondence with said word lines and said data lines, respectively, first selection means for selecting a predetermined word line; second selection means for selecting a predetermined data line; and voltage generation mean for supplying an output voltage to said first selection means, whereby a potential of the selected word line is set substantially at said output voltage, wherein said voltage generation means comprises: signal providing means for providing a signal, switching means for providing said output voltage greater than a predetermined reference voltage in response to said signal, a boost capacitor having a first terminal and a second terminal, said second terminal being coupled to said switching means, a third terminal to which said reference voltage is supplied, precharge means coupled between said second terminal of said boost capacitor and said third terminal, and for precharging said boost capacitor, and voltage limitation means coupled to said signal providing means and for limiting a voltage which is supplied to said first terminal in response to said signal to a predetermined voltage less than said reference voltage.

Claim 39

A semiconductor integrated circuit device according to claim 34, wherein said each memory cell includes a MOSFET and a capacitance element connected thereto.

Claim 40

A semiconductor integrated circuit device according to claim 34, wherein said first selection means comprises a first selector circuit, a second selector circuit and MOSFETs which are coupled between said first selector circuit and said word lines an whose gate are supplied with an output of said second selector circuit, and wherein said output voltage of said voltage generation means is supplied to said first selector circuit.

Claim 41

A semiconductor integrated circuit device according to claim 34, wherein said voltage limitation means comprises a MOSFET coupled to receive said signal at one electrode and for providing said predetermined voltage from another electrode thereof, and wherein a gate of said MOSFET is coupled to a voltage generating means.

Claim 42

A semiconductor integrated circuit device according to claim 37, further comprising control means coupled between a gate of said MOSFET and said voltage generating means.

Claim 43

A semiconductor integrated circuit device according to claim 38, wherein said voltage generating means comprises a first voltage generating means coupled between said control means and a third terminal to which said reference voltage is supplied, and a second voltage generating means coupled between said control means and a fourth terminal to which a second voltage is supplied.

Claim 44

A semiconductor integrated circuit device according to claim 39, wherein said reference voltage is greater than said second voltage.

Claim 45

A semiconductor integrated circuit device according to claim 38, wherein said control means comprises a first diode and a second diode, wherein a first input terminal of said first diode is coupled to a second output terminal of said second diode and a first output terminal of said first diode is coupled to a second input terminal of said second diode, wherein said first input terminal of said first diode is coupled to said voltage limitation means and said first output terminal of said first diode is coupled to said gate of said MOSFET.

Claim 46

A semiconductor integrated circuit device according to claim 41, wherein said first diode and said second diode are constructed of a MOSFET, respectively.

Claim 47

A semiconductor integrated circuit device according to claim 37, wherein said voltage generating means comprises a first voltage generating means coupled between said gate of said MOSFET and a third terminal to which said reference voltage is supplied, and a second voltage generating means coupled between said gate of said MOSFET and a fourth terminal to which a second voltage is supplied.

Claim 48

A semiconductor integrated circuit device according to claim 43, wherein said reference voltage is greater than said second voltage.

Claim 49

A semiconductor integrated circuit device according to claim 34, wherein said precharge means is constructed of at least one MOSFET.

Claim 50

A semiconductor integrated circuit device according to claim 34, wherein said switching means is constructed of a complementary MOSFET.