US4649523A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory with boosted word line
Assignee: Nokia Bell Labs
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Filing: 1985-02-08
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Granted: 1987-03-10
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Expires: 2005-02-08
Abstract
Abstract A dynamic random access memory has a row conductor boosted in excess of the power supply level during an initial portion of a memory cycle. The voltage is then clamped at the supply level during the middle portion of the cycle, and optionally boosted again during the refresh portion. This allows improved performance and reliability, especially in memories employing bit lines precharged to one-half the power supply level.
Inventors
- 👤 Clinton H. Holder, Jr.
- 👤 Howard C. Kirsch
- 👤 James H. Stefany
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:49
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/24; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4085; G11C8/00; G11C8/08
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
155 words
An integrated circuit comprising an array of memory cells adapted to operate at a power supply voltage and arranged in rows and columns, with said memory cells comprising an access transistor and an information storage capacitor, wherein a column conductor is connected to a column of said memory cells and a row conductor is connected to the control terminals of the access transistors in a row of said memory cells; and further comprising row selection means for selecting a given row by applying a row voltage to the row conductor thereof, characterized in that said integrated circuit further comprises means for boosting said row voltage in excess of said power supply voltage during an initial period following said selecting a given row, and for thereafter reducing said row voltage to a level equal to said power supply voltage during a subsequent period of the memory cycle prior to the refresh portion of the memory cycle.
Claim 2
Dependent Claim
155 words
An integrated circuit comprising an array of memory cells adapted to operate at a power supply voltage and arranged in rows and columns, with said memory cells comprising an access transistor and an information storage capacitor, wherein a column conductor is connected to a column of said memory cells and a row conductor is connected to the control terminals of the access transistors in a row of said memory cells; and further comprising row selection means for selecting a given row by applying a row voltage to the row conductor thereof, characterized in that said integrated circuit further comprises means for boosting said row voltage in excess of said power supply voltage during an initial period following said selecting a given row, and for thereafter reducing said row voltage to a level equal to said power supply voltage during a subsequent period of the memory cycle prior to the refresh portion of the memory cycle.
Claim 3
Dependent Claim
23 words
The integrated circuit of claim 1 further comprising means for again boosting said row voltage during the refresh portion of the memory cycle.
Claim 4
Dependent Claim
27 words
The integrated circuit of claim 1 further comprising means for precharging the column conductors of said array to a level approximately one-half of the power supply level.
Claim 5
Dependent Claim
14 words
The integrated circuit of claim 1 further comprising complementary field effect transistor logic circuits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-09 | 1990-09-08 | 1991-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-09 | 1994-09-08 | 1995-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-09 | 1998-09-08 | 1999-03-10 | $7700.00 | Window Closed / Lapsed |