Sloped spacer for MOS field effect devices comprising reflowable glass layer

Claim 1

A method for forming a field effect device for an integrated circuit, comprising the steps of; forming a gate insulating layer over a semiconductor substrate; forming a conductive layer over the gate insulating layer; removing portions of the conductive layer and the gate insulating layer to define a gate electrode for a field effect device; depositing a first, conformal, insulating layer over the substrate and the gate electrode; forming a second insulating layer of reflowable glass over the first insulating layer; heating the glass layer to cause it to partially flow and change slopes of upper surfaces thereof, wherein the slopes of the upper surfaces are more horizontal than a conformally deposited layer above the gate electrode; anisotropically etching the second and first insulating layers to form sidewall spacers alongside the gate electrode, wherein such spacers have an upper surface which approximates the slope of the previous upper surface of the second insulating layer; and implanting impurities into the substrate to form source/drain regions therein, wherein lightly doped drain regions are formed alongside the gate electrode underneath the sidewall spacers by said implanting step, and wherein the lightly doped drain regions have an impurity profile with a shape approximating the slope of the upper surface of the sidewall spacers.

Claim 2

A method for forming a field effect device for an integrated circuit, comprising the steps of; forming a gate insulating layer over a semiconductor substrate; forming a conductive layer over the gate insulating layer; removing portions of the conductive layer and the gate insulating layer to define a gate electrode for a field effect device; depositing a first, conformal, insulating layer over the substrate and the gate electrode; forming a second insulating layer of reflowable glass over the first insulating layer; heating the glass layer to cause it to partially flow and change slopes of upper surfaces thereof, wherein the slopes of the upper surfaces are more horizontal than a conformally deposited layer above the gate electrode; anisotropically etching the second and first insulating layers to form sidewall spacers alongside the gate electrode, wherein such spacers have an upper surface which approximates the slope of the previous upper surface of the second insulating layer; and implanting impurities into the substrate to form source/drain regions therein, wherein lightly doped drain regions are formed alongside the gate electrode underneath the sidewall spacers by said implanting step, and wherein the lightly doped drain regions have an impurity profile with a shape approximating the slope of the upper surface of the sidewall spacers.