Electrically erasable memory device having erase-electrode connected to substrate junction

Claim 2

A nonvolatile semiconductor device, comprising: an array of memory cell transistors, each memory cell transistor comprising: (a) a source diffusion layer and a drain diffusion layer; and (b) a floating gate electrode at least partially overlying a channel region defined by said source and said drain diffusion layer; control gate electrodes, each said control gate electrode partially overlying the floating gate electrode of at least two adjacent memory cell transistors; erasure gate electrode arranged to remove charges from said floating gate electrodes, each said erasure gate electrode being electrically connected to a source diffusion layer substantially equidistant from memory cell transistors having a common control gate electrode; and tunnel oxide films, each tunnel oxide film formed between a side wall of a floating gate electrode and an erasure gate electrode having a common control gate electrode.

Claim 3

The nonvolatile semiconductor device according to claim 1, wherein a source diffusion layer is common to memory cell transistors having a common control gate electrode.

Claim 4

The nonvolatile semiconductor device according to claim 1, wherein said source diffusion layer or drain diffusion layer of each said memory cell transistor comprises a first impurity region having a first concentration located adjacent said channel region and a second impurity region having a second concentration located below said erasure gate electrode, the first concentration being lower than the second concentration.

Claim 5

The nonvolatile semiconductor device according to claim 1, wherein each said tunnel oxide film is formed between the side-wall of a floating gate electrode and a side wall of an erasure gate electrode having a common control gage electrode.

Claim 6

The nonvolatile semiconductor device according to claim 1, wherein charges in each said floating gate move through one of said tunnel oxide films to an erasure gate electrode when a specific potential is applied to said erasure gate electrode.

Claim 7

The nonvolatile semiconductor device according to claim 1, wherein each said erasure gate electrode is common to memory transistors having common control gate electrodes.

Claim 8

The nonvolatile semiconductor device according to claim 1, wherein each source diffusion layer is common to at least two memory cell transistors and wherein each said erasure gate electrode is common to the memory cell transistors in a row of the array which have a common control gate electrodes, and to the memory cell transistors in a column of the array which have a common source diffusion layer.

Claim 9

The nonvolatile semiconductor device according to claim 1, wherein said floating gate electrodes are made from one of polysilicon, silicide, and a stacked structure of both polysilicon and silicide.

Claim 10

The nonvolatile semiconductor device according to claim 1, wherein said control gate electrodes are made from one of polysilicon, silicide, and a stacked structure of polysilicon and silicide.

Claim 11

The nonvolatile semiconductor device according to claim 1, wherein said erasure gate electrodes are made from polysilicon.

Claim 12

The nonvolatile semiconductor device according to claim 1, wherein said tunnel oxide films are made from a polysilicon oxide film.

Claim 13

The nonvolatile semiconductor device according to claim 1, wherein each of said memory cell transistors is further composed of: a semiconductor substrate, said source diffusion layer and drain diffusion layers being formed in a surface region of said semiconductor substrate; a first insulating film formed above said channel region, said floating gate electrode being formed on said first insulating film; and a second insulating film formed on said floating gate electrode, a control gate electrode being formed on said second insulating film.

Claim 14

The nonvolatile semiconductor device according to claim 1, wherein each of said memory cell transistors is further composed of: a semiconductor substrate, said source diffusion layer and drain diffusion layers being formed in a surface region of said semiconductor substrate; a first insulating film formed above said channel region, said floating gate electrode being formed on said first insulating film; and a second insulating film formed on said floating gate electrode, a control gate electrode being formed on said second insulating film near said source diffusion layer.

Claim 15

A nonvolatile semiconductor device, comprising: an array of memory cell transistors, each memory cell transistor comprising a source diffusion layer, a drain diffusion layer common to at least one other memory cell transistor, a floating gate at least partially overlying a channel region defined by the source and drain diffusion layer; control gates, each said control gate overlying at least part of at least two floating gates; erasure gate electrodes arranged to remove charges from said floating gate electrodes, each said erasure gate electrode being electrically connected to a drain diffusion layer at a point substantially equidistant from memory cell transistors having said drain diffusion layer in common; and tunnel oxide films, each said tunnel oxide film being formed between a side wall of a floating gate electrode and an erasure gate electrode which has a common control gate electrode.

Claim 16

A nonvolatile semiconductor device, comprising: an array of memory cell transistors, each memory cell transistor comprising a source diffusion layer, a drain diffusion layer common to at least one other memory cell transistor, a floating gate at least partially overlying a channel region defined by the source and drain diffusion layer; control gates, each said control gate overlying at least part of at least two floating gates; erasure gate electrodes arranged to remove charges from said floating gate electrodes, each said erasure gate electrode being electrically connected to a drain diffusion layer at a point substantially equidistant from memory cell transistors having said drain diffusion layer in common; and tunnel oxide films, each said tunnel oxide film being formed between a side wall of a floating gate electrode and an erasure gate electrode which has a common control gate electrode.

Claim 17

A nonvolatile semiconductor memory device comprising: a semiconductor body; a source region in said semiconductor body; first and second drain regions; first and second floating gate electrodes respectively overlying first and second channel regions defined by said source regions and said first and second drain regions; a control gate electrode at least partially overlying said first and second floating gate electrodes; an erasure gate electrode arranged to remove charges from said first and second floating gate electrodes and being electrically connected to said source region; a first oxide film formed between a side wall of said first floating gate electrode and said erasure gate electrode; and a second oxide film formed between a side wall of said second floating gate electrode and said erasure gate electrode.

Claim 18

A nonvolatile semiconductor memory device comprising: a semiconductor body; a source region in said semiconductor body; first and second drain regions; first and second floating gate electrodes respectively overlying first and second channel regions defined by said source regions and said first and second drain regions; a control gate electrode at least partially overlying said first and second floating gate electrodes; an erasure gate electrode arranged to remove charges from said first and second floating gate electrodes and being electrically connected to said source region; a first oxide film formed between a side wall of said first floating gate electrode and said erasure gate electrode; and a second oxide film formed between a side wall of said second floating gate electrode and said erasure gate electrode.

Claim 19

A nonvolatile semiconductor device comprising: an array of memory cell transistors, arranged in rows and columns, the memory cell transistors in each adjacent pair of columns having a common source diffusion layer, and each memory cell transistor having a drain diffusion layer and a floating gate electrode at least partially overlying a channel region defined by said common source diffusion layer and said drain diffusion layer; control gate electrodes respectively overlying the floating gate electrodes of memory cell transistors in a column of said array; bit lines respectively connected to the drain diffusion layers of memory cell transistors in a row of said array; erase gate electrodes respectively provided for one of a plurality of memory cell transistor groups, each said memory cell transistor group being constituted by four memory cell transistors where each memory cell transistor in a memory transistor group is adjacent to two of the other three memory cell transistors in the group, wherein each of the erasure gate electrodes is provided for removing charges from the floating gate electrodes of the four memory cell transistors in the corresponding memory cell transistor group, and wherein each of the erasure gate electrodes is connected to a source diffusion layer common to the four memory cell transistors at a position which is substantially equidistant from connections between the drain diffusion layers of the four memory cell transistors and their corresponding bit lines; and a plurality of tunnel oxide films, one each being formed between and in contact with a side wall of the floating gate electrodes and the erasure gate electrodes in a memory cell transistor group.

Claim 20

A nonvolatile semiconductor device comprising: an array of memory cell transistors, arranged in rows and columns, the memory cell transistors in each adjacent pair of columns having a common source diffusion layer, and each memory cell transistor having a drain diffusion layer and a floating gate electrode at least partially overlying a channel region defined by said common source diffusion layer and said drain diffusion layer; control gate electrodes respectively overlying the floating gate electrodes of memory cell transistors in a column of said array; bit lines respectively connected to the drain diffusion layers of memory cell transistors in a row of said array; erase gate electrodes respectively provided for one of a plurality of memory cell transistor groups, each said memory cell transistor group being constituted by four memory cell transistors where each memory cell transistor in a memory transistor group is adjacent to two of the other three memory cell transistors in the group, wherein each of the erasure gate electrodes is provided for removing charges from the floating gate electrodes of the four memory cell transistors in the corresponding memory cell transistor group, and wherein each of the erasure gate electrodes is connected to a source diffusion layer common to the four memory cell transistors at a position which is substantially equidistant from connections between the drain diffusion layers of the four memory cell transistors and their corresponding bit lines; and a plurality of tunnel oxide films, one each being formed between and in contact with a side wall of the floating gate electrodes and the erasure gate electrodes in a memory cell transistor group.

Claim 21

The nonvolatile semiconductor device according to claim 16, wherein each of said source diffusion layers which are common to the memory cell transistors in each adjacent pair of columns of said array comprises: a first impurity region having a first dopant concentration and which is located near the channel region; and a second impurity region having a second dopant concentration and which is located below the erasure gate electrode, said first dopant concentration being lower than said second dopant concentration.

Claim 22

The nonvolatile semiconductor device according to claim 16, wherein charges in the floating gate electrodes of the four memory cell transistors of each of said memory cell transistor groups move through tunnel oxide films which are in contact with side walls of the floating gate electrodes when a specific potential is applied to the erasure gate electrode for each four memory cell transistors.

Claim 23

The nonvolatile semiconductor device according to claim 16, wherein each said floating gate electrode in said array of memory cell transistors is made from one of polysilicon, silicide, and a stacked structure of both polysilicon and silicide.

Claim 24

The nonvolatile semiconductor device according to claim 16, wherein said plurality of control gate electrodes are made from one of a group consisting of polysilicon, silicide, and a stacked structure of polysilicon and silicide.

Claim 25

The nonvolatile semiconductor device according to claim 16, wherein said plurality of erasure gate electrodes are made from polysilicon.

Claim 26

The nonvolatile semiconductor device according to claim 16, wherein each tunnel oxide film in said array of memory cell transistors is made from polysilicon oxide film.

Claim 27

A non-volatile semiconductor memory device, comprising: a semiconductor body; first and second current terminal regions in said semiconductor body; a first insulating film over said semiconductor body; a floating gate electrode on said first insulating film and overlying a channel region between said first and second current terminal regions; a second insulating film on said floating gate electrode; a control gate electrode formed on said second insulating film and overlying said floating gate electrode; a bit line coupled to the second current terminal region; an erase gate electrode for discharging said floating gate electrode and having an outermost side wall portion laterally spaced from and facing a side wall portion of said floating gate electrode; and a tunnel oxide film sandwiched between the side wall portion of said floating gate electrode and said outermost side wall portion of said erase gate electrode.

Claim 28

A non-volatile semiconductor memory device, comprising: a semiconductor body; first and second current terminal regions in said semiconductor body; a first insulating film over said semiconductor body; a floating gate electrode on said first insulating film and overlying a channel region between said first and second current terminal regions; a second insulating film on said floating gate electrode; a control gate electrode formed on said second insulating film and overlying said floating gate electrode; a bit line coupled to the second current terminal region; an erase gate electrode for discharging said floating gate electrode and having an outermost side wall portion laterally spaced from and facing a side wall portion of said floating gate electrode; and a tunnel oxide film sandwiched between the side wall portion of said floating gate electrode and said outermost side wall portion of said erase gate electrode.

Claim 29

The nonvolatile semiconductor device according to claim 23, wherein said erase gate electrode contacts said first current terminal region.

Claim 30

The nonvolatile semiconductor device according to claim 23, wherein said tunnel oxide film comprises a polysilicon oxide film.

Claim 31

A non-volatile semiconductor memory device, comprising: first and second terminal regions of a row and column array of memory cell transistors; a first insulating film; floating gate electrodes formed on said first insulating film and overlying channel regions between respective ones of said first and second current terminal regions; a second insulating film formed on said floating gate electrodes; control gate electrodes formed on said second insulating film and overlying the floating gate electrodes of memory cell transistor in respective columns of said array; bit lines coupled to the second current terminal regions of the memory cell transistors in respective rows of said array; erase gate electrodes each having a first portion disposed between end portions of first and second adjacent floating gate electrodes in a first column of said array and a second portion disposed between end portions of first and second adjacent floating gate electrodes in a second column of said array; and tunnel oxide films sandwiched between the end portions of said floating gate electrodes and side walls of said first and second portions of said erase gate electrodes.

Claim 32

A non-volatile semiconductor memory device, comprising: first and second terminal regions of a row and column array of memory cell transistors; a first insulating film; floating gate electrodes formed on said first insulating film and overlying channel regions between respective ones of said first and second current terminal regions; a second insulating film formed on said floating gate electrodes; control gate electrodes formed on said second insulating film and overlying the floating gate electrodes of memory cell transistor in respective columns of said array; bit lines coupled to the second current terminal regions of the memory cell transistors in respective rows of said array; erase gate electrodes each having a first portion disposed between end portions of first and second adjacent floating gate electrodes in a first column of said array and a second portion disposed between end portions of first and second adjacent floating gate electrodes in a second column of said array; and tunnel oxide films sandwiched between the end portions of said floating gate electrodes and side walls of said first and second portions of said erase gate electrodes.

Claim 33

The nonvolatile semiconductor device according to claim 26, wherein said first current terminals comprise current terminals common to memory cell transistors in adjacent columns of said array.

Claim 34

The nonvolatile semiconductor device according to claim 27, wherein said first current terminals comprise source terminals.

Claim 35

The nonvolatile semiconductor device according to claim 28, wherein said erase gate electrodes are in contact with the source terminal common to the first and second column of said array.

Claim 36

The nonvolatile semiconductor device according to claim 28, wherein said source terminals each comprise a low-concentration region adjacent said channels and a high concentration region in contact with said erase gate electrodes.

Claim 37

The nonvolatile semiconductor memory device according to claim 26, wherein said control gate electrodes have an offset structure relative to said floating gate electrodes such that a first portion of said control gate electrodes overlies said floating gate electrodes and a second portion of said control gate electrodes in spaced from said channel regions by said first insulating film.