Patent US5228045A successfully refreshed from Google Patents.
US5228045A
Expired / Lapsed
US
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Test driver for connecting a standard test port integrated circuit chip to a controlling computer
Assignee: NCR Voyix Corp
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Filing: 1990-08-06
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Granted: 1993-07-13
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Expires: 2010-08-06
Abstract
Abstract A test driver for connecting a controlling computer to an IC chip having a standard test access port (TAP) is both hardware and software efficient. The last stage of a wrap-around or circulating control register feeds a test mode select (TMS) pin of the TAP, and feeds the next-to-the-last stage back to the first stage. As a result of the control register configuration, the control register's original contents are automatically restored after each shift, cycle, thus abrogating the need to reload the control register if the same control pattern is again needed, and abrogating the need to maintain (via software) the correct value on the TMS pin in between shifting sequences of the control register. Proper shift times in a data register of the test driver are achieved by replicating the IC chip TAP controller state machine.
Inventors
- 👤 Wilton R. Chiles
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:45
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31905; G01R31/3185; G01R31/318533; G01R31/318555
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
187 words
A test driver for coupling a controlling computer to an under-test integrated circuit (IC) chip having a standard test access port (TAP) with at least a test mode select (TMS) pin and a standard test access port controller (TAPC), said test driver comprising: a data register coupled to said controlling computer, and coupled to test data input (TDI) and test data output (TDO) pins of said TAP, said register receiving test data from said computer for transfer to said IC via said TDI pin and receiving data from said IC via said TDO pin for transfer to said computer; and a wrap-around control register, having a number of shift stages and connected between said controlling computer and said TMS pin, for storing control information received from said controlling computer, said control register having a first end stage coupled to said TMS pin and a second end stage on the end opposite said first end stage coupled to a stage other than said first end stage for circulating the information with each shift, so that the previously loaded control information is restored after a shifting cycle is complete.
Claim 2
Dependent Claim
187 words
A test driver for coupling a controlling computer to an under-test integrated circuit (IC) chip having a standard test access port (TAP) with at least a test mode select (TMS) pin and a standard test access port controller (TAPC), said test driver comprising: a data register coupled to said controlling computer, and coupled to test data input (TDI) and test data output (TDO) pins of said TAP, said register receiving test data from said computer for transfer to said IC via said TDI pin and receiving data from said IC via said TDO pin for transfer to said computer; and a wrap-around control register, having a number of shift stages and connected between said controlling computer and said TMS pin, for storing control information received from said controlling computer, said control register having a first end stage coupled to said TMS pin and a second end stage on the end opposite said first end stage coupled to a stage other than said first end stage for circulating the information with each shift, so that the previously loaded control information is restored after a shifting cycle is complete.
Claim 3
Dependent Claim
49 words
The test driver in claim 1 further comprising a TAP state machine coupled to the first end stage of said control register and coupled to said data register to clock and place said data register in a shift mode when said TAP state machine is in a "shift" state.
Claim 4
Dependent Claim
77 words
The test driver in claim 2 further comprising a decrementing control counter coupled to said controlling computer and coupled to said control register, wherein said control counter is loaded with a number equal to the number of shift stages of said control register minus one, sends shift control signals to said control register causing said control register to shift, decrements after each shift until said control counter reaches zero, and then ceases to send shift control signals.
Claim 5
Dependent Claim
37 words
The test driver in claim 2 wherein said data register has a number of stages and wherein the number of stages in said control register is 4 more than the number of stages in said data register.
Claim 6
Dependent Claim
77 words
The test driver in claim 1 further comprising a decrementing control counter coupled to said controlling computer and coupled to said control register, wherein said control counter is loaded with a number equal to the number of shift stages of said control register minus one, sends shift control signals to said control register causing said control register to shift, decrements after each shift until said control counter reaches zero, and then ceases to send shift control signals.
Claim 7
Dependent Claim
37 words
The test driver in claim 5 wherein said data register has a number of stages and wherein the number of stages in said control register is 4 more than the number of stages in said data register.
Claim 8
Dependent Claim
37 words
The test driver in claim 1 wherein said data register has a number of stages and wherein the number of stages in said control register if 4 more than the number of stages in said data register.
Claim 9
Dependent Claim
179 words
A test driving method for coupling a controlling computer to an under-test integrated circuit (IC) chip having a standard test access port (TAP) with at least a test mode select (TMS) pin and a standard test access port controller (TAPC), said test driving method comprising the steps of: with a data register coupled to said controlling computer, and coupled to test data input (TDI) and test data output (TDO) pins of said TAP, transferring test data from said register to said IC via said TDI pin and transferring data from said IC to said register via said TDO pin; storing control information received from said controlling computer in a wrap-around control register, said control register having a number of shift stages and connected between said computer and said TMS pins, wherein a first end stage is coupled to said TMS pin, and a second end stage is coupled to a stage other than said first end stage; and circulating the information with each shift, so that the previously loaded control information is restored after a shifting cycle is complete.
Claim 10
Dependent Claim
179 words
A test driving method for coupling a controlling computer to an under-test integrated circuit (IC) chip having a standard test access port (TAP) with at least a test mode select (TMS) pin and a standard test access port controller (TAPC), said test driving method comprising the steps of: with a data register coupled to said controlling computer, and coupled to test data input (TDI) and test data output (TDO) pins of said TAP, transferring test data from said register to said IC via said TDI pin and transferring data from said IC to said register via said TDO pin; storing control information received from said controlling computer in a wrap-around control register, said control register having a number of shift stages and connected between said computer and said TMS pins, wherein a first end stage is coupled to said TMS pin, and a second end stage is coupled to a stage other than said first end stage; and circulating the information with each shift, so that the previously loaded control information is restored after a shifting cycle is complete.
Claim 11
Dependent Claim
57 words
The test driving method in claim 8 further comprising the step of clocking and placing said data register in a shift mode by a TAP state machine when said TAP state machine is in a "shift" mode, said TAP state machine coupled to the first end stage of said control register and coupled to said data register.
Claim 12
Dependent Claim
84 words
The test driving method in claim 9 further comprising the steps of: loading a decrementing control counter coupled to said controlling computer and coupled to said control register with a number equal to the number of shift stages of said control register minus one; sending shift control signals to said control register causing said control register to shift; decrementing said control counter after each shift until said control counter reaches zero; and ceasing to send shift control signals when said control counter reaches zero.
Claim 13
Dependent Claim
38 words
The test driving method in claim 9 wherein said data register has a number of stages and wherein the number of stages in said control register is 4 more than the number of stages in said data register.
Claim 14
Dependent Claim
84 words
The test driving method in claim 8 further comprising the steps of: loading a decrementing control counter coupled to said controlling computer and coupled to said control register with a number equal to the number of shift stages of said control register minus one; sending shift control signals to said control register causing said control register to shift; decrementing said control counter after each shift until said control counter reaches zero; and ceasing to send shift control signals when said control counter reaches zero.
Claim 15
Dependent Claim
38 words
The test driving method in claim 12 wherein said data register has a number of stages and wherein the number of stages in said control register is 4 more than the number of stages in said data register.
Claim 16
Dependent Claim
38 words
The test driving method in claim 8 wherein said data register has a number of stages and wherein the number of stages in said control register is 4 more than the number of stages in said data register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-12 | 1997-01-11 | 1997-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-12 | 2001-01-11 | 2001-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-12 | 2005-01-11 | 2005-07-13 | $7700.00 | Window Closed / Lapsed |