US4291386A
Expired / Lapsed
US
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Pseudorandom number generator
Assignee: Unisys Corp
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Filing: 1980-02-04
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Granted: 1981-09-22
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Expires: 2000-02-04
Abstract
Abstract An apparatus for testing digital logic circuits without a computer and associated software employs a psuedorandom stream of input data to produce an unstructured output data stream which is analyzed by an efficient data collector and analyzer. Test signal generation is implemented by a pseudorandom number generator and a pseudorandom clock/reset generator while the resulting test data at the output terminals of the device under test is analyzed by a cycle redundancy code checker. Fault localization is realized, with selectable localization and manual probe modes and circuitry is provided for an efficient self-test mode.
Inventors
- 👤 David S. Bass
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 05:18
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/31813; G01R31/319; G01R31/31917; G01R31/31919; G01R31/31921; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/277
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
164 words
A pseudorandom number generator comprising: shift register means having tap means at each stage thereof, data input means and clock input means; K bit modulo two adder means coupled at input means thereof to K selected tap means of said shift register means and at output means thereof to said data input means of said shift register means; register means with each stage thereof coupled correspondingly to said tap means of said shift register means, said register means having tap means at each stage thereof and clock input means; and means coupled between said clock input means of said shift register means and said clock input means of said register means for providing a clock pulse to said clock input means after a preselected number of clock pulses have been applied to said clock input means of said shift register means whereby after each clock pulse applied to said register means a data code is available at said tap means of said register means.
Claim 2
Dependent Claim
164 words
A pseudorandom number generator comprising: shift register means having tap means at each stage thereof, data input means and clock input means; K bit modulo two adder means coupled at input means thereof to K selected tap means of said shift register means and at output means thereof to said data input means of said shift register means; register means with each stage thereof coupled correspondingly to said tap means of said shift register means, said register means having tap means at each stage thereof and clock input means; and means coupled between said clock input means of said shift register means and said clock input means of said register means for providing a clock pulse to said clock input means after a preselected number of clock pulses have been applied to said clock input means of said shift register means whereby after each clock pulse applied to said register means a data code is available at said tap means of said register means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-21 | 1985-03-23 | 1985-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-21 | 1989-03-23 | 1989-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-21 | 1993-03-23 | 1993-09-22 | $7700.00 | Window Closed / Lapsed |